Claire Xen 🏳️‍⚧️ 🧙🏻‍♀️ 💖💛💙

So if you are currently involved with ISA-level decisions about inclusion of any pext/pdep-like instructions:

Please consider including SAG/inverse-SAG with bit-reversal of the goats.

No matter which of the two implementation methods you are using: All you need to do is not mask the goat bits.

So if you are currently involved with ISA-level decisions about inclusion of any pext/pdep-like instructions:

Please consider including SAG/inverse-SAG with bit-reversal of the goats.

No matter which of the two implementation methods you are using: All you need to do is not mask the goat bits.

At some point that patent will expire, and until then there's my implementation.

(And I think my approach will still stay relevant after, because it makes it very simple to build multi-cycle SAG cores.)

I think the really important takeaway is that they, my method and theirs, are both functionally the same, i.e. they both implement an SAG with bit-reversal of the goats.

This means, as far as the ISA is concerned, it's a safe decision to include an SAG instruction.

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... back to normal ^__^

Nah! No luck. 🙈 I was unsure which of the 4 options I could come up with to pick, and as it turned out, it was none of them... 😂

But I'm still at 99% and that's all that really matters to me. (But tbh, it does matter to me way more than it probably should..)

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... Wahhh! I have ~23 hours to decide on a last guess... /o\

Here is the code:
github.com/clairexen/ed...

I can't see any obvious reason why that identity should not extend beyond 8-bit units. But I have not actually tested that hypothesis yet.

I have to make a correction regarding ☝️. I've now implemented the Hilewitz-Lee method as well in my edu-sag repository. And it implements the bit-reflecting-SAG as-is. All you have to do is to remove the '&ci' from the data input, thus it's always more area to implement PEXT than bit-reflecting-SAG.

Here is the code:
github.com/clairexen/ed...

I can't see any obvious reason why that identity should not extend beyond 8-bit units. But I have not actually tested that hypothesis yet.

I have to make a correction regarding ☝️. I've now implemented the Hilewitz-Lee method as well in my edu-sag repository. And it implements the bit-reflecting-SAG as-is. All you have to do is to remove the '&ci' from the data input, thus it's always more area to implement PEXT than bit-reflecting-SAG.

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.. that was a bit unusual.
but I still got it in the end ^__^

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edu-sag/param.v at main · clairexen/edu-sag Educational 8-Bit Sheep-And-Goats (SAG) Verilog Reference IP - clairexen/edu-sag

I wrote a reference implementation for a SAG without bit reflection: github.com/clairexen/ed..., and I wrote a parametric SAG core for any bit width: github.com/clairexen/ed...

edu-sag/param.v at main · clairexen/edu-sag Educational 8-Bit Sheep-And-Goats (SAG) Verilog Reference IP - clairexen/edu-sag

I wrote a reference implementation for a SAG without bit reflection: github.com/clairexen/ed..., and I wrote a parametric SAG core for any bit width: github.com/clairexen/ed...

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... that one was fun

To have trans friends is to hold candles in the wind.

I can’t say if the storm is fate or man-made.

I only know I’m losing light.

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For R-type instructions there's not much pressure there...

The wire crossings are there either way. It's literally the same network graph, just organized differently in the HDL, so that it's easier to see how similar the three stages of circuit are.

..cost of the mask operation. At least IMO.

Thought-Experiment:

Would you rather have

1) SAG plus MaskedSAG, or

2) SAG plus all 4 PACK Instructions?

I'd certainly pick 2) and for most architectures it's even cheaper in terms of hardware cost than 1)... 🤔

But isn't it also "basically free" in software? It's literally just one instruction. ;)

On a superscalar OOO machine I think it'd be unlikely that one is bottle-necked by the additional mask op.

For an instruction like this one, what really matters is the avoided cost of ~500 cycles, not the..

Yes, I mean the definition of SAG with the mirroring. The non-mirrored version is way more expensive (and IMO actually less desirable anyway).

I just wrote this:
github.com/clairexen/ed...

I've been meaning to write this code for quite some time...

And those symmetries then can be exploited for things from re-use of completed layouts for functional units, to creating different multi-cycle versions of SAG HDL cores.

I think it's better to use just the first stage of the (inverse) butterfly network and unshuffle, like I did it here, than to use an actual (inv) butterfly network, because this way it's much easier to understand all the symmetries within such an SAG HW implementation.

Yes, I mean the definition of SAG with the mirroring. The non-mirrored version is way more expensive (and IMO actually less desirable anyway).

I just wrote this:
github.com/clairexen/ed...

I've been meaning to write this code for quite some time...

If you don't do the (infamously patented) pruning of the prefix sum network, then SAG is the natural behavior of that kind of bfly/ibfly based pext/pdep Implementation.

Afair the Hilewitz06 paper only adds that you can get rid of some of the half adders if you don't care about goat bits order.. 🤔