I bought two of these boards in 2016, one for a friend one for me. I forgot about mine until last night.

Not yet it literally arrived this morning so I rushed to the office. But forgot it was the weekend they are changing internet providers so no net to do any work.

Quite impressed with the PCBite range from sensepeek. Came across them on a random tweet, it give the ability to probe with scopes, drive, observe digital signals and of course power boards hands free. Perfect for production test.

MicroZed Chronicles: ChipScoPy When it comes to debugging designs the more visibility and control we have over debugging elements such as ILAs is critical. When we are working with AMD Versal device such as Versal Prime, Edge or Co...

The ability to debug our FPGA applications is critical. This week I am looking at ChipScoPy, which enables us to leverage Python and Jupyter notebooks to work with ILAs, VIO and the hard debug peripherals in Versal devices.

www.adiuvoengineering.com/post/microze...

I thoroughly enjoyed this webinar yesterday.

www.youtube.com/watch?v=5Q6K...

looking forward to what @ataylorfpga.bsky.social comes up with for next years webinars 🫡

Fridays are for demos, so check out our latest Hackster project which shows how we can use a Arty A7, with MicroBlaze V, and Jupyter Labs to create a really cool robot arm demo we can control from our PC or program and replay sequences also

www.hackster.io/adam-taylor/...

Altera Agilex 5E Premium Development Kit and NIOS V In our last instalment we configured the tool chain and started the creation of the example design for the Agilex 5E Premium development kit. This is a good starting point as it provides us with a NIO...

Taking a look at creating an example design on the Agilex 5E development board.
#fpga #engineering #embeddedsystems #electronics #embeddedsoftware
www.adiuvoengineering.com/post/altera-...

MicroZed Chronicles: DSP58 and FP32 Mode Last week we examined how we could use the IEEE VHDL 2008 fixed and floating packages to implement a simple polynomial approximation. As discussed previously the DSP58 is capable of operating in a FP3...

Looking this week at using a Vitis HLS to implement a DSP58 in FP32 mode

www.adiuvoengineering.com/post/microze...

Altera Agilex 5 Setting up the tool chain Over this series of blogs we have explored the Altera Agilex 5 devices and their architecture. Of course nothing beats getting hands on with a device and its tool chain so in this article we are going...

Taking a look at setting up the Agilex 5E tool chain and license.
www.adiuvoengineering.com/post/altera-...

I am very impressed with how Vitis Unified using the HLS flow has been able to target to the Versal DSP58 in FP32 mode for the equation I was implementing in last weeks blog. Significantly less resources than required using the native VHDL 2008 float package.

MicroZed Chronicles: Fixed and Floating Point Maths A short time ago I hosted a webinar which looked at how we can implement mathematics within programmable logic. In this webinar we examined how we could create mathematics applications using RTL, HLS ...

This week I was taking a look at the differences in resources required to implement the same algorithm when using the VHDL 2008 fixed and floating point packages.

www.adiuvoengineering.com/post/microze...

Always wanted do Jury service but never have. I am an expert witness in a patent cases and that clashes with a conference I want to go to next year. Enjoy Supercomputing.

MicroZed Chronicles: Fixed and Floating Point Maths A short time ago I hosted a webinar which looked at how we can implement mathematics within programmable logic. In this webinar we examined how we could create mathematics applications using RTL, HLS ...

Last week we ran a webinar on implementing maths in FPGA. One of the attendees asked the question what the difference in implementation size would be between fixed and floating point.

#fpga #embeddedsystems #engineering #embeddedsoftware #engineering

www.adiuvoengineering.com/post/microze...