A z80 DIP-packaged CPU in an semi-isometric view, the top of the chip facing front (the chip is standing on its side), with gold pins at the top and the letters "Z80" on the front.

Have a pixel art 8-bit CPU!

#pixelart #z80 #retrocomputing

It was very common for stuff to do direct register access, which the BIOS wouldn't be able to translate.

a scan of the bottom of Seequa Chameleon's RAM expansion board - the 2 layer board allows the top traces to be visible through the board itself due to the bright light source above it.

if you scan a 2 layer PCB on a flatbed scanner with a bright light source above it, it kinda looks like an X-ray.

#retrocomputing

They actually stuck an 8250 UART on their "RAMPlus" expansion card (the 8250 being the "plus") which is a bit of a last-ditch compatibility play.

Also most of the Chameleon is basically PC compatible except for one key peripheral - they went with the Intel 8274 serial controller. Bad call for them, considering most PC software assumed the 8250 UART that IBM chose for the PC.

Secondly, and more importantly I guess, was lack of EMF shielding and mitigation that made running a Chameleon akin to operating an unlicensed radio station, and got them sued by the FCC - the FCC actually raided their liquidation auction to stop them from selling the remaining Chameleons!

It's an impressive machine, but a few combination of factors killed it - not putting ISA slots in the base model Chameleon was a bad call, ignoring the explosion of expansion cards that made the IBM PC ecosystem what it was. They offered an expansion chassis, but IBM couldn't sell that idea either.

If Seequa ever wanted to adjust the wait states for RAM or ship faster CPUs with the same RAM, all they needed to do was reprogram this PAL - no reworking a complicated mess of wait state generation logic like is found on the IBM 5150 and 5160.

There's a PAL called "DCON" that controls the main READY signal (and thus creates wait states), and it gets the /88_PRIMARY signal, and a signal from the IO decoder when VRAM or SRAM is being read.

There's a million other details that are very clever, I could go on and on.

The Z80 is clocked at half the rate of the 8088. But the DMA clock remains constant - they took advantage of the on-board floppy controller to use the 16MHz crystal to derive the timings for DMA, VRAM and SRAM.

a screenshot of the root page of the Seequa Chameleon schematic in kicad. Colorful bus lines connected hierarchical schematic pages positioned roughly in their real-world locations on the motherboard

I did something with the KiCad schematics that is sure to either please or horrify you.

All the hierarchical sheets are placed in their physical positions where those units exist on the motherboard. Not every unit is a perfect square, but it gives you the idea.

Meanwhile, the "DMA" PAL translates the Z80's bus arbitration signals to the 8088's and back, so the CPUs can hand off the bus to each other.

the two main bus-logic PALS, "80ST" and "DMA" on the Chameleon, side by side. The main post discusses most of their logic.

The other is used for bus arbitration with the Z80. But the Z80 uses a slightly different mechanism, two separate pins /BUSREQ and /BUSACK.

The job of the 80ST PAL is to convert the Z80's bus status pins into the S0-S2 signals compatible with the Intel 8288 bus controller.

Anyway, it's also not enough to just yank the bus from the inactive CPU, it is really ideal if they know they don't have the bus anymore.

The 8088 has two RQ/GT pins for this purpose, allowing it to have two co-processors (how convenient!). One of them is used for the 8087.

The hardware was certainly capable of delivering on this promise, but would have required a more sophisticated BIOS. It wasn't storage constraints either considering the Chameleon has a ridiculous 6 ROM sockets that can be configured for up to 16K EPROMS.

Seequa somewhat implied you could just insert any CP/M disk and have the Chameleon run it in Z80 mode, but not how it panned out, as reviewers of the time noted with some frustration. The only real accommodation in the BIOS is support for CP/M formatted diskettes.

All hardware interrupts are serviced by the 8088. The CP/M boot loader diskette contains the logic to resume execution after interrupt processing - this was not automatic.

the 74LS173 4-bit register that supplies the upper 4 address lines for the Z80 when it is operating.

The Z80's reset vector is 0000h, so it would, without intervention, start trying to execute the 8088's interrupt vector table.

So naturally, a page register is supplied to provide the upper four address lines, allowing you to let the Z80 run in any of 16 64KB segments.

Any idea how the bus is managed between the 2 CPUs to avoid contention?

KiCad again showing the 74LS138 octal decoder that selects from CGA registers and - also swaps between the 8088 and Z80. Sure, why not.

How you actually request a CPU swap was something Seequa changed their mind about late - they actually tied a bodge wire to this address decoder in the video unit.

Just reading or writing to port 3DEh swaps between the 8088 and Z80. The CPX pal will wait until the end of any INT or LOCK.

a kicad schematic showing a 74LS157 with the /88_PRIMARY input on the left and separate /AEN pins for each CPU's buffers exiting right.

The /88_PRIMARY signal drives the relative AEN lines for each CPU - as you can see the way this thing is wired up, it's like a flip flop between the two CPUs, feeding in +5V to turn off the relevant address buffers if that CPU is not selected.

a screenshot of KiCad showing the "CPX" pal chip with various inputs such as the CPU clock, LOCK and INTR pins, and a special input called the "CPU SWAP STROBE". Its outputs include the RESET signal and the CPU select signal "/88_PRIMARY"

I do! Figuring out how all that worked was my first goal. The KiCad schematics have the fully traced CPU logic unit.

The heart of it is this PAL16R8 chip labelled "CPX" I've called it CPU eXchange.

It emits the /88_PRIMARY signal - the inverse of which, of course, means the Z80 has the bus.

GitHub - dbalsom/seequa_chameleon: Reverse engineering of the Seequa Chamelon PC Reverse engineering of the Seequa Chamelon PC. Contribute to dbalsom/seequa_chameleon development by creating an account on GitHub.

Everything is freely available here in the name of preserving this machine from obscurity.

github.com/dbalsom/seeq...

Also check out @mcjonestech.com 's excellent Seequa archive:

seequa.org

I won't claim that the result is going to be a reproduction-ready motherboard - Seequa did some really wild shit routing this board.

The size and complexity of the board makes it being only two layers just slightly insane. A proper reproduction board should probably switch to four.

a photo of the backside of a Chameleon motherboard showing numerous bodge wires run all over the place

I've also been reworking the PCB to incorporate many of the bodge wires Seequa put on the machine at the factory.

photo credit: @mcjonestech.com

If the motherboard looks a bit sparse in the lower-right corner, you're not wrong. Down there is the floppy controller, and it has a PLL with about eighty billion resistors I am not looking forward to tracing out an measuring.

( do not trust 40 year old resistor color bands)

a screenshot of the "PALchemy" utility, interactively analyzing the PAL12L6 chip that handles NMI and interrupt logic on the Seequa Chameleon. Inputs are labelled beside a SVG of a DIP chip, with red LEDs simulating outputs at a logically high TTL voltage.

I wrote this tool to investigate the workings of its PAL chips - it ended up that twiddling the inputs and watching the outputs was a bit more intuitive for me to grasp than just staring at equation dumps.

a screenshot of KiCad's 3D viewer showing the current state of GloriousCow's Seequa Chameleon motherboard reverse-engineering project. a large green PCB is shown with lots of different components.

What do you do when you want to emulate a computer system that has no schematics and very little documentation?

You just reverse-engineer the entire motherboard with KiCad, of course.

This is the Seequa Chameleon, a dual-CPU IBM PC clone luggable machine from 1983.

#retrocomputing #emulation

no u

PALchemy: a new PAL dumping and chip analysis utility I'm working on. Interactively poke chip pins! All you need is a T48 USB programmer.

#retrocomputing