arXiv cs.AR Hardware Architecture

Yuhao Liu, Salim Ullah, Akash Kumar: Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators https://arxiv.org/abs/2602.23334 https://arxiv.org/pdf/2602.23334 https://arxiv.org/html/2602.23334

Guangyu Hu, Xiaofeng Zhou, Wei Zhang, Hongce Zhang: EvolveGen: Algorithmic Level Hardware Model Checking Benchmark Generation through Reinforcement Learning https://arxiv.org/abs/2602.22609 https://arxiv.org/pdf/2602.22609 https://arxiv.org/html/2602.22609

Yuhao Liu, Salim Ullah, Akash Kumar: GRAU: Generic Reconfigurable Activation Unit Design for Neural Network Hardware Accelerators https://arxiv.org/abs/2602.22352 https://arxiv.org/pdf/2602.22352 https://arxiv.org/html/2602.22352

Daksha, Guzelhan, Shivdikar, Domingo, Lopez, Jonatan, Dymarkowski, Jerari, Cano, Abell\'an, Kim, Kaeli, Joshi: FHECore: Rethinking GPU Microarchitecture for Fully Homomorphic Encryption https://arxiv.org/abs/2602.22229 https://arxiv.org/pdf/2602.22229 https://arxiv.org/html/2602.22229

[2026-02-27 Fri (UTC), 4 new articles found for csAR Hardware Architecture]

Wang, Yan, Liu, Upton, Cai, Tan, Li, Jana, Li, Cirimelli-Low, Tambe, Guthaus, Wong: Heterogeneous Memory Design Exploration for AI Accelerators with a Gain Cell Memory Compiler https://arxiv.org/abs/2602.21278 https://arxiv.org/pdf/2602.21278 https://arxiv.org/html/2602.21278

[2026-02-26 Thu (UTC), 1 new article found for csAR Hardware Architecture]

Philippos Papaphilippou: LUTstructions: Self-loading FPGA-based Reconfigurable Instructions https://arxiv.org/abs/2602.20802 https://arxiv.org/pdf/2602.20802 https://arxiv.org/html/2602.20802

Hongyi Guan, Yijia Zhang, Wenqiang Wang, Yizhao Gao, Shijie Cao, Chen Zhang, Ningyi Xu: TOM: A Ternary Read-only Memory Accelerator for LLM-powered Edge Intelligence https://arxiv.org/abs/2602.20662 https://arxiv.org/pdf/2602.20662 https://arxiv.org/html/2602.20662

Rakshith Jayanth, Viktor Prasanna: FAST-Prefill: FPGA Accelerated Sparse Attention for Long Context LLM Prefill https://arxiv.org/abs/2602.20515 https://arxiv.org/pdf/2602.20515 https://arxiv.org/html/2602.20515

Da Chen, Guangyu Hu, Kaihong Xu, Kaichao Liang, Songjiang Li, Wei Yang, XiangYu Wen, Mingxuan Yuan: SegSEM: Enabling and Enhancing SAM2 for SEM Contour Extraction https://arxiv.org/abs/2602.20471 https://arxiv.org/pdf/2602.20471 https://arxiv.org/html/2602.20471

[2026-02-25 Wed (UTC), 4 new articles found for csAR Hardware Architecture]

Li, Vardar, M\"uller, Goli, Tida, Ni, Hu, K\"ampfe, Qin: CQ-CiM: Hardware-Aware Embedding Shaping for Robust CiM-Based Retrieval https://arxiv.org/abs/2602.20083 https://arxiv.org/pdf/2602.20083 https://arxiv.org/html/2602.20083

Ilan Rosenfeld, Noam Kleinburd, Hillel Chapman, Dror Reuven: Hardware-Friendly Randomization: Enabling Random-Access and Minimal Wiring in FHE Accelerators with Low Total Cost https://arxiv.org/abs/2602.19550 https://arxiv.org/pdf/2602.19550 https://arxiv.org/html/2602.19550

Zhang, Yin, Gangi, Chen, Bamfo, Xu, Gu, Huang: SKYLIGHT: A Scalable Hundred-Channel 3D Photonic In-Memory Tensor Core Architecture for Real-time AI Inference https://arxiv.org/abs/2602.19031 https://arxiv.org/pdf/2602.19031 https://arxiv.org/html/2602.19031

Harry Fitchett, Jasmine Ritchie, Charles Fox: Extending CPU-less parallel execution of lambda calculus in digital logic with lists and arithmetic https://arxiv.org/abs/2602.19884 https://arxiv.org/pdf/2602.19884 https://arxiv.org/html/2602.19884

Xiaoke Wang, Raveena Raikar, Markus Rein, Ruiqi Chen, Chang Meng, Dirk Stroobandt: Interconnect-Aware Logic Resynthesis for Multi-Die FPGAs https://arxiv.org/abs/2602.19720 https://arxiv.org/pdf/2602.19720 https://arxiv.org/html/2602.19720

Irisha M. Goswami, D. G. Perera: Closed-Loop Environmental Control System on Embedded Systems https://arxiv.org/abs/2602.19305 https://arxiv.org/pdf/2602.19305 https://arxiv.org/html/2602.19305

Sonu Kumar, Mohd Faisal Khan, Mukul Lokhande, Santosh Kumar Vishvakarma: CORVET: A CORDIC-Powered, Resource-Frugal Mixed-Precision Vector Processing Engine for High-Throughput AIoT applications https://arxiv.org/abs/2602.19268 https://arxiv.org/pdf/2602.19268 https://arxiv.org/html/2602.19268

Zheng Li, Guangyi Zeng, Paul Delestrac, Enyi Yao, Simei Yang: pHNSW: PCA-Based Filtering to Accelerate HNSW Approximate Nearest Neighbor Search https://arxiv.org/abs/2602.19242 https://arxiv.org/pdf/2602.19242 https://arxiv.org/html/2602.19242

Md Rownak Hossain Chowdhury, Mostafizur Rahman: A Logic-Reuse Approach to Nibble-based Multiplier Design for Low Power Vector Computing https://arxiv.org/abs/2602.19007 https://arxiv.org/pdf/2602.19007 https://arxiv.org/html/2602.19007

He Sun, Li Li, Mingjun Xiao: HillInfer: Efficient Long-Context LLM Inference on the Edge with Hierarchical KV Eviction using SmartSSD https://arxiv.org/abs/2602.18750 https://arxiv.org/pdf/2602.18750 https://arxiv.org/html/2602.18750

Matthew Adiletta, Gu-Yeon Wei, David Brooks: RPU -- A Reasoning Processing Unit https://arxiv.org/abs/2602.18568 https://arxiv.org/pdf/2602.18568 https://arxiv.org/html/2602.18568

[2026-02-24 Tue (UTC), 8 new articles found for csAR Hardware Architecture]

Mohammad Farahani, Mohammad Rasoul Roshanshah, Saeed Safari: Flexi-NeurA: A Configurable Neuromorphic Accelerator with Adaptive Bit-Precision Exploration for Edge SNNs https://arxiv.org/abs/2602.18140 https://arxiv.org/pdf/2602.18140 https://arxiv.org/html/2602.18140

Gwenevere Frank, et al.: HiAER-Spike Software-Hardware Reconfigurable Platform for Event-Driven Neuromorphic Computing at Scale https://arxiv.org/abs/2602.18072 https://arxiv.org/pdf/2602.18072 https://arxiv.org/html/2602.18072

[2026-02-23 Mon (UTC), 2 new articles found for csAR Hardware Architecture]

Kathiravan Palaniappan: GDEV-AI: A Generalized Evaluation of Deep Learning Inference Scaling and Architectural Saturation https://arxiv.org/abs/2602.16858 https://arxiv.org/pdf/2602.16858 https://arxiv.org/html/2602.16858

Yogeswar Reddy Thota, Setareh Rafatirad, Homayoun Houman, Tooraj Nikoubin: When Models Ignore Definitions: Measuring Semantic Override Hallucinations in LLM Reasoning https://arxiv.org/abs/2602.17520 https://arxiv.org/pdf/2602.17520 https://arxiv.org/html/2602.17520

Yuhuan Xia, Tun Li, Hongji Zhou, Xianfa Zhou, Chong Chen, Ruiyu Zhang: SimulatorCoder: DNN Accelerator Simulator Code Generation and Optimization via Large Language Models https://arxiv.org/abs/2602.17169 https://arxiv.org/pdf/2602.17169 https://arxiv.org/html/2602.17169