Underfox

Today is Intel's anniversary. I sincerely hope that Intel can recover from these difficult times and rid itself of the real culprits for its problems who are still on its board of directors.

This work provides insights into key subsystems including the memory hierarchy, SM execution pipelines, and the SM subcore units, including the 5th generation tensor cores that support FP4 and FP6 precisions.

In this paper is presented a detailed experimental analysis of NVIDIA’s Blackwell architecture through microbenchmarks with a comparison to the previous Hopper generation GPUs.

arxiv.org/pdf/2507.10789

The researchers interpret these results as being fermion parity switches, arguing that these results are the first demonstration of two distinct projective measurements of fermion parity in a tetron device.

To date, none of the claims have been properly peer-reviewed.

The results show that the minimum observed single-shot measurement-errors are 0.5% for the Z loop and 16% for the X loop. Continuous monitoring of the two measurements reveals distinct characteristic timescales of τZ = 12.4 ± 0.4 ms and τX = 14.5 ± 0.3 μs.

Microsoft Quantum researchers have presented a hardware realization and measurements of a tetron qubit device in a superconductor-semiconductor heterostructure, which support four Majorana zero modes (MZMs) when tuned into the topological phase.

arxiv.org/pdf/2507.08795

The Fractile analog AI accelerator: Going beyond the von Neumann paradigm In the world of semiconductors, it should come as no surprise to hear about the numerous benefits of using analog in-memory computing, which promises significantly better peak performance and energy e...

My last article mentions a direct application of these principles, which have a strong tendency to intensify in the near future.

underfox3.substack.com/p/the-fracti...

By relaxing the constraints needed for traditional ASICs, these devices aim to operate as exact realizations of physical processes, offering substantial gains in energy efficiency and computational throughput.

The basic idea of the proposed framework is essentially to make this largely unintentional trend in the last 20 years fully intentional and principled.

In this paper is proposed Physics-based ASIC, a transformative paradigm that directly leverages the physical dynamics intrinsic to computation, rather than expending resources to impose idealized digital abstractions.

arxiv.org/pdf/2507.10463

The results show that the Josephson FeFET can be used as a cryogenic superconducting non-volatile single memory cell, maintaining excellent state retention and readout stability over 24 hours of continuous measurement.

The new proposed device was fabricated on the InAsOI hybrid platform, where an InAs epilayer was grown onto a cryogenic electrical insulating substrate, employing HfO2 as the gate insulator, which introduces ferroelectricity.

In this paper, researchers have demonstrated the ferroelectric behavior of a hybrid superconducting Josephson Fe-FET operating at a cryogenic sub-K temperature.

arxiv.org/pdf/2507.04773

The experimental results on realistic 2D and 3D masks show that the WGNO achieves state-of-the-art accuracy and inference time, providing a highly efficient solution for accelerating the design workflows of lithography masks.

In this paper is introduced a hybrid Waveguide Neural Operator, a novel neural operator to solve the EUV diffraction problem, replacing only the most computationally intensive part of the WG method with a neural network.

arxiv.org/pdf/2507.04153

In this paper is introduced the HLStrans, the first large-scale dataset of over 23K paired C and HLS programs harvested from academic repositories for LLM-powered HLS code synthesis from software.

arxiv.org/pdf/2507.04315

NeuroPDE achieves a variance of less than 1e-2 compared to analytical solutions when solving diffusion equations, showing 3.48x to 315x speedup in execution time and an energy consumption advantage of 2.7× to 29.8× over advanced CMOS-based neuromorphic chips (Loihi and TrueNorth).

The proposed design features neurons with probabilistic activation, winner-takes-all, and self-inhibitory functions, and synapses that can store weights continuously.

In this paper is proposed NeuroPDE, a hardware design for neuromorphic PDE solvers which exploit the intrinsic physical randomness of MTJ devices to create a scalable neuromorphic architecture capable of performing random walk functions.

arxiv.org/pdf/2507.04677

As I said 5 years ago, I repeat it today: The future of graphics is directly linked to neural rendering.

archive.is/rOJIx

The results show that Neuralocks achieves efficient runtime computations with limited memory requirements, outperforming state-of-the-art approaches.

The proposed method is based in a novel direct mapping between boundary condition history and strand deformations, significantly simplifying the training procedure and inference compared to prior work while maintaining dynamic results that react naturally to body movement.

Meta researchers have developed Neuralocks, a novel method that achieves high-performance dynamic neural hair simulation with a compact network size.

arxiv.org/pdf/2507.05191

GitHub - facebookresearch/any4: Quantize transformers to any learned arbitrary 4-bit numeric format Quantize transformers to any learned arbitrary 4-bit numeric format - facebookresearch/any4

GitHub ANY4

github.com/facebookrese...

The results show that accuracy of any4 is superior to other 4-bit numeric formats with low memory overhead, and competitive with various orthogonal quantization techniques that involve further pre-processing.

Meta researchers have developed ANY4, a learned 4-bit weight quantization solution for large language models, providing arbitrary numeric representations without requiring pre-processing of weights or activations.

arxiv.org/pdf/2507.04610

By treating reliability as a tunable system parameter rather than a fixed hardware constraint, the proposed design opens a new path toward low-cost, high-performance HBM deployment for AI infrastructure.

The evaluation using LLM inference workloads shows that, even under raw HBM bit error rates up to 10−3, the proposed system retains over 78% of throughput and 97% of model accuracy compared with systems equipped with ideal error-free HBM.

n this paper is proposed a hybrid ECC architecture that pairs large-size Reed–Solomon codes with fine-grained CRC, allowing to reduce HBM cost by shifting fault tolerance from HBM stack to the system level.

arxiv.org/pdf/2507.02654

"These results represent a significant advancement in the generation of high-energy, ultrashort deep UV pulses, opening new possibilities for emerging applications in semiconductor science, quantum materials, and photochemistry."