Underfox

This structure maximizes rendering speed and compression, because it is not necessary to further compute or store new pyramid levels to provide LOD, but rather simply mask out parts of the same asset to naturally obtain a continuous representation, spectrally-wise.

Gabor Fields is the first pure primitive-based volumetric model that can naturally decompose not only into different frequency bands, but that is also orientation-selective.

In this paper is proposed Gabor Fields, a new volumetric primitive fields that enables continuous frequency filtering at no cost, enabling continuous LoD control, reduced rendering time, and a trade-off between variance and bias for performance.

arxiv.org/pdf/2602.05081

CVA6-CFI design incurs in only 1.0% area overhead when synthesized in 22FDX technology, and up to 15.6% performance overhead based on evaluation with the MiBench automotive benchmark subset.

In this paper is presented CVA6-CFI, the first design, integration, and evaluation of the standard #RISC-V extensions for Control-Flow Integrity, introducing 2 independent hardware units implementing backward-edge and forward-edge control-flow protection.

arxiv.org/pdf/2602.04991

In this paper, researchers have analyzed the neural scaling behavior for a high-dimensional spectroscopic learning task using over 200k ab initio dielectric functions, finding the emergence of broken neural scaling in the field of materials science.

arxiv.org/pdf/2602.05702

This is the the first example that ferroelectricity and ultrahigh carrier density coexist within the same spatial region.

In this paper, researchers have demonstrated the coexistence of room-temperature out-of-plane ferroelectricity and metallic conductivity with ultrahigh carrier density in atomically thin TaNiTe5.

arxiv.org/pdf/2602.05398

These findings reinforce the common understanding that hardware acceleration (via GPU, FPGA, or ASIC) is not optional for LDPC 5G decoding at realistic iteration counts and reliability targets.

When translated into per-codeword latency, Grace CPU decoding can exceed the 0.5 ms NR slot at 20 iterations, while GB10 remains within 24% of the slot at the same operating point and as low as 6% at fewer iterations.

The results show a consistent GPU/CPU throughput speedup of approximately 6x, with individual configurations ranging between about 5.5x and 6.3x.

In this paper is presented an empirical study of LDPC 5G decoding on an NVIDIA DGX Spark, comparing execution on the Grace CPU and the integrated Blackwell GB10 GPU using a Sionna PHY/SYS implementation of a 5G NR–like link-level chain.

arxiv.org/pdf/2602.04652

Overall, Crypto-RV achieves a high flexibility with minimal area overhead, sustains high-throughput computation through hierarchical buffering, and eliminates memory stalls via continuous double-buffering, transforming crypto operations from memory- to compute-bound execution.

The evaluation results show that Crypto-RV achieves 165x to 1,061x speedup over baseline RISC-V cores, 5.8x to 17.4x better energy efficiency compared to powerful CPUs.

In this paper is presented Crypto-RV, a RISC-V coprocessor architecture that unifies support for SHA-256, SHA-512, SM3, SHA3-256, SHAKE-128, SHAKE-256 AES-128, HARAKA-256, and HARAKA-512 within a single 64-bit datapath. #RISCV

arxiv.org/pdf/2602.04415

In this paper, researchers have demonstrated that Pna21/ CaSnN2 is a potential alternative to InxGa1−xN
in blue LEDs and for the technology of adding a yellow phosphorescent coating for white LEDs.

arxiv.org/pdf/2602.04106

The overall analysis of the results presented shows that a laminated vertical design with dual-gate control effectively enhances the stability of nanoscale transistors, highlighting their potential for next-generation low-power logic, memory, and flexible electronics.

The proposed device shows a low off-state current of ≈1 pA at 3 V, an on/off ratio exceeding 105, and high output currents of ≈1 mA cm−2 at 0.1 V and ≈50 mA cm−2 at 1 V, while maintaining a threshold voltage within ±0.5 around 0 V.

The device architecture featuring a fully encapsulated channel, micro-hole patterned source electrode, and a graphene drain, enabled complementary gate field modulation across the entire channel, effectively suppressing leakage currents and ensuring stable V_th control.

Researchers have demonstrated a dual-modulated vertical transistor with a leakage-blocking layer, fabricated through a simple stacked process without the need for high-resolution alignment or costly techniques, even at nanoscale channel lengths.

advanced.onlinelibrary.wiley.com/doi/epdf/10....

In this thread, I will highlight some of the works that will be presented in February at ISSCC 2026. The following thread highlights some of the most interesting works of this year. There are a lot of interesting news on the way...

Advance Program: submissions.mirasmart.com/ISSCC2026/PD...

In this paper is proposed HetCCL, the first cross-vendor collective communication library that enables DL model training and inference on heterogeneous clusters with both NVIDIA and AMD GPUs.

arxiv.org/pdf/2601.22585

These work show that strain provides a practical knob to control band structure and valley topology in moiré graphene.

Researchers have presented a comprehensive analysis of the tight-binding properties of twisted and strained bilayer graphene, revealing a strong dependence of band narrowing and topology on strain type, magnitude, direction and lattice relaxation.

arxiv.org/pdf/2602.02692

In this paper is presented a rigorous error analysis of the Ozaki-II scheme, showing the accuracy behavior of the method and enabling the estimation of the number of low-precision matrix mult. required to achieve a desired level of numerical accuracy. #HPC

arxiv.org/pdf/2602.02549

Phoenix delivers robust speedups in the baseline configuration (up to 2.88x) and remains competitive, and often faster, even in the stronger precision regime (up to 2.91x), without a systematic runtime penalty.

By decoupling algorithmic concerns from infrastructure, Phoenix aims to accelerate both research prototyping and the development of production-grade tools for C/C++ programs.

In this paper is presented Phoenix, a modular pointer analysis framework for C/C++ that unifies multiple state-of-the-art alias analysis algorithms behind a single, stable interface.

arxiv.org/pdf/2602.01720

Underfox3 | Substack Independent tech analyst focused on semiconductors, patent analysis and emerging technologies. Click to read Underfox3, a Substack publication. Launched a year ago.

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This work has been submitted for review for presentation at ICML2026. We will have updates soon, including the launch of the repository.