RascalFoxfire aka. the funky CPU fox

Aaaaaaand i shifted focus again on my magic compiler. Well, at least i should be then able to make something useful for my 16 bit OoOE CPUs. And if i get that running i also have directly a toolchain for my large SuperSatellit 16 bit CPU

Btw. the ROB is messy but works quite well. But you can see here why implicit renaming designs weren't much of a thing and why explicit renaming is the name of the games today

Ladies and gentlemens: my OoOE CPU executed its first instructions and in parallel! Seems like i got all the routing and control issues out. Next will be the memory unit and branches. It is still a POS since it got some inconvenient flaws but i guess that it is still very solid for a first OoOE CPU

Lesson learned, ROBs in data-in-ROB CPUs are messy. Every entry needs to listen on my 5 CDB lines + the 4 commit stages. Meaning i need 9 x 24 (instructions my ROB can handle) comparators, 24 9-way encoders and MUXes and more stuff. Now i know why we use PRF designs today instead

My brain decided to multitask back to the OoOE 16 bit CPU... well, i managed to build the commit bus to the reservation stations (needed in case a finished value is send to the ROB, a follow up instruction depends on it but the value wasn't yet commited to the register file). Next into the ROB!

Build a little more on the 16 bit RISC CPU. Interrupts should run now (i hope). Gonna test it tomorrow. The compiler is coming along quite nicely but still slow going

Finished the config file, onward to the actual compiler. Still deep within the code

Still on the compiler. I nearly finished writing the config file for the Companion CPU. Meanwhile i started implementing a project safe/load feature into the actual compiler

Got a first logisim implementation of CompanionNISC in its most basic BI32 variant! It doesn't even have the register file extensions but that is was the plan. Very simple, still quite powerful. Time to build some software and compare it with a RISC-V 32I!

Not much from my side, still on going easy on programming. Progress is slow since i burned out a little from all the hardware tinkering

Okay, compilerwise i started implementing the first modules to get from my custom IR to the target arch. Currently suprisingly smooth riding

Okay, a little more spoiling: i am creating an universal compiler which you can feed a simple .json with your ISAs instruction and behaviour and then does the rest without much intervention. That is why i am going this route. But fair, i could at that point prob even use something like LLVM

Ah okay, i understood. Well that was the initial idea: start with the current universal assembler and then putting the compiler on top. But i am derivating here since i need a custom IR for some suprise that will help us later. Can't spoil too much rn since it is still all just could/should/hope

Ah thank you! Well, i got an assembler running but there is quite a lot more to the story since the compiler will be also a technological demonstrator for something that looks quite promising (for short: universal compiler). But any help is welcome and i will definitely make a deep dive into yours!

Not ded but quite busy. Currently on my compiler to get finally some test software on my CPUs without going to hexadecimal and/or assembler again

Thanks for the double reminder...

Okay, i am half back mentally. Focus shifted back to the Pico-Series of ISAs and subsequent CPUs but now i am back at the 16 bit CPU to finish the interrupt and ring system!

Back from the east with some fresh energy to continue! Time to get back to original business: the large 16 bit CPU with floating point stuff!

Going offline for the weekend, got into an adventure to an old GDR bunker. But before that i shall share the following wisdome i just learned: implicit renaming is funny on paper but bad in hardware, go explicit on your adventures. Tune in next time!

Tinkered a little on the 4-way implicit renaming CPU variant. The 2-way in order CPU uses the same ISA. I only need the load store unit, the reorder buffer, a smart instruction dispatcher and later the branch prediction system from the in order CPU. Next CPU in that series will use explicit renaming

Quite some easy days here. Did a little more on the super scalar CPUs, managed to write a lil on the GPU ISA and even started to implement the interrupts into my large 16 bit CPU

Small update: started the FPU edge case detection for my large 16 bit CPU, build a lil on the branch prediction for the in order CPU and managed to start the OoOE 16 bit CPU based on the in order CPU. I guess 4 input instruction pipelines are enough for the OoOE experiment

YES!!! Ladies and gentlemen, my first functional super scalar CPU! It still lacks the jump/branch and memory operations but i managed to get the first operations run parallely. I also managed to include operand forwarding with cross pipeline forwarding and pipeline swap compensation! What an act...

I need to add that the ISA for that 16 bit CPU is incredible simple. It has only 16 instructions: 4 Mul/Div, 4 ALU, 4 Jump/Branch, 2 Util (MOV, LDI) and 2 Mem. No interrupts, no ring modes, no CPU control register, no nothing. Just a simple ISA to test how super scalarity works in general

ye, the regfile, oh dear... i am quite concerned how later OoOE CPUs with IPCs over 4 do it but i guess for PRF designs you start doing set associative stuff. Interpipeline hazards are already mostly dealt with, only (cross pipeline) operand forwarding should be an issue. And thanks for the paper!

Did a lil in the super scalar experimental department with the simple 16 bit ISA. Inspired by the Motorola 68060 i started building it with two pipelines, one supporting the full ISA (A) while the second (B) won't have a Mul/Div and Jump/Branch unit. They can even swap instructions when needed!

agreed, we need moar fennecs!

Did a lil on the FPU today, still an endless fight. Did also quickly design a very simple 16 bit RISC ISA to test some accelerating technologies like in order and out of order superscalarity since my previous attempt went wrong

Sitting currently on my logisim FPU, soon i will start fixing my terminal driver in SysVerilog and later maybe tinker a lil on Picoalchemist, the larger brother of my tiny 8 bit RISC Picowizard

Small update: got the signed short to float16 and vice versa converter of my FPU ready. Next an extension to the MMU and the FPU adder/subtractor