Want to help build a crowdsourced microcontroller?
You're invited to design peripherals (UARTs, timers, synths, etc.) for a @riscv.org.web.brid.gy chip that will be fabbed for real!
Take part for free!
tinytapeout.com/competitions...
@yosyshq.com.bsky.social
The home for the team maintaining Yosys and related Open Source EDA projects. https://www.yosyshq.com/ Sign up to our newsletter! https://yosyshq.com/newsletter
Want to help build a crowdsourced microcontroller?
You're invited to design peripherals (UARTs, timers, synths, etc.) for a @riscv.org.web.brid.gy chip that will be fabbed for real!
Take part for free!
tinytapeout.com/competitions...
We have a new home for community discussion around Yosys
yosyshq.discourse.group
Join us there for questions, support and discussion about our open source EDA tools.
#community #opensource #Yosys
We have a new home for community discussion around Yosys
yosyshq.discourse.group
Join us there for questions, support and discussion about our open source EDA tools.
#community #opensource #Yosys
Yes, if yosys and friends didn't exist I probably wouldn't have done any HW side projects, so i'd never have started Spade or Surfer
04.06.2025 15:47 β π 4 π 1 π¬ 0 π 0My thesis is now published online! π
urn.kb.se/resolve?urn=...
IHP25b - our 4th open source chip with IHP is now open for digital design submissions!
Weβre very happy to have our next shuttle open and weβre already looking forward to seeing another great set of designs manufactured onto custom silicon!
Weβre close to making key decisions about future shuttlesβand we want your input! π¬
What features matter most? Whatβs your price ceiling?
Take our 2-min survey π forms.gle/EMrSJQ6dmw4P...
π One respondent will win a beautiful 150mm silicon wafer!
Bad AAPL
10.04.2025 06:43 β π 13521 π 4092 π¬ 194 π 146Good news open-source #FPGA fans, there's a new release of nextpnr (place and route) from @yosyshq.com. The release notes mention "Numerous improvements to Gowin support": github.com/YosysHQ/next...
24.03.2025 10:37 β π 15 π 3 π¬ 0 π 0Join us in a few hours for a talk about ASIC synthesis with Yosys!
18:00 CET / 22:30 IST / 09:00 PT
meet.jit.si/yosys-users-...
Emil will be covering:
* ASIC synthesis in general
* Yosys scripts
* abc scripts
* New Yosys features for ASIC
Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 20th.
Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/
It's time for another YUG! What's a YUG? It's the Yosys User's Group! For anyone interested in using Yosys - we've had sessions on primitives, plugins, hardware security, FPGAs and lots more...
This time we'll be turning to #ASIC synthesis with our own Emil JiΕΓ Tywoniak.
Simulation is the #ASIC terminology of the week!
In the last month, Simulation has been the 35th most popular out of 42 terms.
Looking for a tiny RISC-V core that scales with your needs?
We covered FazyRV by Meinhard Kissich in our community spotlight last year: blog.yosyshq.com/p/community-...
Now it's been silicon proven on @tinytapeout.com !
www.linkedin.com/posts/meinha...
Insta-follow, nice! Looking forward to your dive in to interesting off the main path of @yosyshq.com bit.
Gonna have to figure out what other fpga/yosys/openfpga nerds there are to follow here that I'm missing!
Fearlessly generate your own clocks with Lattice ECP5 #FPGAs and Yosys. Includes worked examples for #ULX3S and easy to adapt to any dev board. Happy #FPGAFriday! @yosyshq.com projectf.io/posts/ecp5-f...
31.01.2025 09:42 β π 8 π 4 π¬ 0 π 0Yosys and nextpnr have excellent support for Lattice ECP5 FPGAs. However, without using the ECP5 PLL (phase-locked loop), you're stuck running at the speed of your dev board oscillator. This post outlines the frequency capabilities of the ECP5 PLL and provides several practical examples to get you started with generating custom clock frequencies.
Working on a new #FPGA blog post this evening. I'll be sharing the draft with my sponsors in the next few days. @yosyshq.com
"Yosys and nextpnr have excellent support for Lattice ECP5 FPGAs. However, without using the ECP5 PLL, you're stuck running at the speed of your dev board oscillator..."
I taped out a variety of adders on open source silicon and Kogge-Stone adders were the fastest for all widths above 8 bits.
Yosys now has plugins to choose which topology you want! Read more here: www.zerotoasiccourse.com/post/instrum...
Very cool work by courk.cc ! Laser fault injection rig used to defeat RP2350 secure boot.
Lovely writeup, interactive 3d model views, and uses the open source Glasgow FPGA multitool!
courk.cc/rp2350-chall...
Have you ever wondered how Yosys prepares your design for an #FPGA? In the next Yosys Users Group, our own Krystine will walk us through the synth_ice40 command, how it works and what's going on behind the scenes!
Monday 16th December at 9:00 PT / 18:00 CET / 22:30 IST
To get a reminder on the day, join the newsletter: blog.yosyshq.com/newsletter/
09.12.2024 11:25 β π 0 π 0 π¬ 0 π 0Have you ever wondered how Yosys prepares your design for an #FPGA? In the next Yosys Users Group, our own Krystine will walk us through the synth_ice40 command, how it works and what's going on behind the scenes!
Monday 16th December at 9:00 PT / 18:00 CET / 22:30 IST
At the beginning of the year Gabriel Gouvine wrote a guest blog post for us about his logic locking plugin for Yosys.
He taped out a locked design on Tiny Tapeout 6 and we've just tested it!
Blog: blog.yosyshq.com/p/logic-lock...
youtu.be/m7MlQ2k8xC8
After a summer break, our user group meetings have resumed again!
In our last call, Katharina CeesaySeitz from ETH ZΓΌrich presented her work to detect microarchitectural information leakage via hardware timing side channels.
Watch her talk on our Youtube channel!
www.youtube.com/watch?v=Kxp-...
Video of @mattvenn.net MPW1 chip
20.11.2024 23:27 β π 8 π 2 π¬ 0 π 01st post on bluesky!
18.11.2024 16:19 β π 39 π 11 π¬ 3 π 0