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YosysHQ

@yosyshq.com.bsky.social

The home for the team maintaining Yosys and related Open Source EDA projects. https://www.yosyshq.com/ Sign up to our newsletter! https://yosyshq.com/newsletter

293 Followers  |  10 Following  |  10 Posts  |  Joined: 18.11.2024  |  1.8201

Latest posts by yosyshq.com on Bluesky

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Want to help build a crowdsourced microcontroller?

You're invited to design peripherals (UARTs, timers, synths, etc.) for a @riscv.org.web.brid.gy chip that will be fabbed for real!

Take part for free!

tinytapeout.com/competitions...

25.07.2025 10:57 β€” πŸ‘ 55    πŸ” 34    πŸ’¬ 2    πŸ“Œ 3
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We have a new home for community discussion around Yosys

yosyshq.discourse.group

Join us there for questions, support and discussion about our open source EDA tools.

#community #opensource #Yosys

09.06.2025 11:50 β€” πŸ‘ 7    πŸ” 2    πŸ’¬ 0    πŸ“Œ 0
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We have a new home for community discussion around Yosys

yosyshq.discourse.group

Join us there for questions, support and discussion about our open source EDA tools.

#community #opensource #Yosys

09.06.2025 11:50 β€” πŸ‘ 7    πŸ” 2    πŸ’¬ 0    πŸ“Œ 0

Yes, if yosys and friends didn't exist I probably wouldn't have done any HW side projects, so i'd never have started Spade or Surfer

04.06.2025 15:47 β€” πŸ‘ 4    πŸ” 1    πŸ’¬ 0    πŸ“Œ 0
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My thesis is now published online! πŸŽ‰

urn.kb.se/resolve?urn=...

03.06.2025 12:23 β€” πŸ‘ 24    πŸ” 9    πŸ’¬ 3    πŸ“Œ 0
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IHP25b - our 4th open source chip with IHP is now open for digital design submissions!

We’re very happy to have our next shuttle open and we’re already looking forward to seeing another great set of designs manufactured onto custom silicon!

25.04.2025 10:08 β€” πŸ‘ 4    πŸ” 2    πŸ’¬ 2    πŸ“Œ 0
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We’re close to making key decisions about future shuttlesβ€”and we want your input! πŸ’¬

What features matter most? What’s your price ceiling?

Take our 2-min survey πŸ‘‰ forms.gle/EMrSJQ6dmw4P...

🎁 One respondent will win a beautiful 150mm silicon wafer!

15.04.2025 08:40 β€” πŸ‘ 18    πŸ” 6    πŸ’¬ 0    πŸ“Œ 0
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Bad AAPL

10.04.2025 06:43 β€” πŸ‘ 13521    πŸ” 4092    πŸ’¬ 194    πŸ“Œ 146
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Release nextpnr 0.8 Β· YosysHQ/nextpnr Remove nextpnr-gowin; replaced by Gowin support in nextpnr-himbaechel Remove unmaintained FPGA interchange support Updated and reworked CMake build system Himbaechel: Numerous improvements to Gowin...

Good news open-source #FPGA fans, there's a new release of nextpnr (place and route) from @yosyshq.com. The release notes mention "Numerous improvements to Gowin support": github.com/YosysHQ/next...

24.03.2025 10:37 β€” πŸ‘ 15    πŸ” 3    πŸ’¬ 0    πŸ“Œ 0
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Join us in a few hours for a talk about ASIC synthesis with Yosys!

18:00 CET / 22:30 IST / 09:00 PT

meet.jit.si/yosys-users-...

20.02.2025 13:17 β€” πŸ‘ 3    πŸ” 2    πŸ’¬ 0    πŸ“Œ 0
Newsletter Sign up to our newsletter and don't miss a post!

Emil will be covering:

* ASIC synthesis in general
* Yosys scripts
* abc scripts
* New Yosys features for ASIC

Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 20th.

Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/

18.02.2025 17:40 β€” πŸ‘ 0    πŸ” 0    πŸ’¬ 0    πŸ“Œ 0
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It's time for another YUG! What's a YUG? It's the Yosys User's Group! For anyone interested in using Yosys - we've had sessions on primitives, plugins, hardware security, FPGAs and lots more...

This time we'll be turning to #ASIC synthesis with our own Emil JiΕ™Γ­ Tywoniak.

18.02.2025 17:40 β€” πŸ‘ 5    πŸ” 1    πŸ’¬ 1    πŸ“Œ 0
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Simulation Simulation is the ASIC terminology of the week!

Simulation is the #ASIC terminology of the week!
In the last month, Simulation has been the 35th most popular out of 42 terms.

03.02.2025 19:00 β€” πŸ‘ 8    πŸ” 1    πŸ’¬ 0    πŸ“Œ 0
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Looking for a tiny RISC-V core that scales with your needs?

We covered FazyRV by Meinhard Kissich in our community spotlight last year: blog.yosyshq.com/p/community-...

Now it's been silicon proven on @tinytapeout.com !

www.linkedin.com/posts/meinha...

03.02.2025 11:39 β€” πŸ‘ 12    πŸ” 7    πŸ’¬ 0    πŸ“Œ 0

Insta-follow, nice! Looking forward to your dive in to interesting off the main path of @yosyshq.com bit.

Gonna have to figure out what other fpga/yosys/openfpga nerds there are to follow here that I'm missing!

21.01.2025 19:37 β€” πŸ‘ 2    πŸ” 1    πŸ’¬ 0    πŸ“Œ 0
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ECP5 FPGA Clock Generation Yosys and nextpnr have excellent support for Lattice ECP5 FPGAs. However, without using the ECP5 PLL (phase-locked loop), you’re stuck running at the speed of your dev board oscillator. This post outl...

Fearlessly generate your own clocks with Lattice ECP5 #FPGAs and Yosys. Includes worked examples for #ULX3S and easy to adapt to any dev board. Happy #FPGAFriday! @yosyshq.com projectf.io/posts/ecp5-f...

31.01.2025 09:42 β€” πŸ‘ 8    πŸ” 4    πŸ’¬ 0    πŸ“Œ 0
Yosys and nextpnr have excellent support for Lattice ECP5 FPGAs. However, without using the ECP5 PLL (phase-locked loop), you're stuck running at the speed of your dev board oscillator. This post outlines the frequency capabilities of the ECP5 PLL and provides several practical examples to get you started with generating custom clock frequencies.

Yosys and nextpnr have excellent support for Lattice ECP5 FPGAs. However, without using the ECP5 PLL (phase-locked loop), you're stuck running at the speed of your dev board oscillator. This post outlines the frequency capabilities of the ECP5 PLL and provides several practical examples to get you started with generating custom clock frequencies.

Working on a new #FPGA blog post this evening. I'll be sharing the draft with my sponsors in the next few days. @yosyshq.com

"Yosys and nextpnr have excellent support for Lattice ECP5 FPGAs. However, without using the ECP5 PLL, you're stuck running at the speed of your dev board oscillator..."

21.01.2025 18:36 β€” πŸ‘ 24    πŸ” 7    πŸ’¬ 1    πŸ“Œ 0

I taped out a variety of adders on open source silicon and Kogge-Stone adders were the fastest for all widths above 8 bits.

Yosys now has plugins to choose which topology you want! Read more here: www.zerotoasiccourse.com/post/instrum...

18.01.2025 18:52 β€” πŸ‘ 22    πŸ” 6    πŸ’¬ 3    πŸ“Œ 0
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Laser Fault Injection on a Budget: RP2350 Edition In August 2024, Raspberry Pi introduced the RP2350 microcontroller. This part iterates over the RP2040 and comes with numerous new features. These include security-related capabilities, such as a Secu...

Very cool work by courk.cc ! Laser fault injection rig used to defeat RP2350 secure boot.

Lovely writeup, interactive 3d model views, and uses the open source Glasgow FPGA multitool!

courk.cc/rp2350-chall...

19.01.2025 18:41 β€” πŸ‘ 17    πŸ” 2    πŸ’¬ 0    πŸ“Œ 0
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Have you ever wondered how Yosys prepares your design for an #FPGA? In the next Yosys Users Group, our own Krystine will walk us through the synth_ice40 command, how it works and what's going on behind the scenes!

Monday 16th December at 9:00 PT / 18:00 CET / 22:30 IST

09.12.2024 11:25 β€” πŸ‘ 13    πŸ” 7    πŸ’¬ 1    πŸ“Œ 0
Newsletter Sign up to our newsletter and don't miss a post!

To get a reminder on the day, join the newsletter: blog.yosyshq.com/newsletter/

09.12.2024 11:25 β€” πŸ‘ 0    πŸ” 0    πŸ’¬ 0    πŸ“Œ 0
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Have you ever wondered how Yosys prepares your design for an #FPGA? In the next Yosys Users Group, our own Krystine will walk us through the synth_ice40 command, how it works and what's going on behind the scenes!

Monday 16th December at 9:00 PT / 18:00 CET / 22:30 IST

09.12.2024 11:25 β€” πŸ‘ 13    πŸ” 7    πŸ’¬ 1    πŸ“Œ 0
Logic Locking plugin on silicon works!
YouTube video by YosysHQ Logic Locking plugin on silicon works!

At the beginning of the year Gabriel Gouvine wrote a guest blog post for us about his logic locking plugin for Yosys.

He taped out a locked design on Tiny Tapeout 6 and we've just tested it!

Blog: blog.yosyshq.com/p/logic-lock...

youtu.be/m7MlQ2k8xC8

03.12.2024 15:30 β€” πŸ‘ 11    πŸ” 3    πŸ’¬ 0    πŸ“Œ 0
yug8
YouTube video by YosysHQ yug8

After a summer break, our user group meetings have resumed again!

In our last call, Katharina CeesaySeitz from ETH ZΓΌrich presented her work to detect microarchitectural information leakage via hardware timing side channels.

Watch her talk on our Youtube channel!

www.youtube.com/watch?v=Kxp-...

26.11.2024 11:31 β€” πŸ‘ 9    πŸ” 2    πŸ’¬ 0    πŸ“Œ 0
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Video of @mattvenn.net MPW1 chip

20.11.2024 23:27 β€” πŸ‘ 8    πŸ” 2    πŸ’¬ 0    πŸ“Œ 0

1st post on bluesky!

18.11.2024 16:19 β€” πŸ‘ 39    πŸ” 11    πŸ’¬ 3    πŸ“Œ 0

@yosyshq.com is following 10 prominent accounts