Charles Eric LaForest, PhD

Thanks. I'm glad it's useful to you! As for the pointers, you remind me that I should post the CDC version of this FIFO, which indeed does non-2^N pointers across clock domains, without using Grey Codes. ;)

good luck with your projects!

I have an open client slot for FPGA design consulting: fpgacpu.ca/gateforge/in...

Over the last 9 years, I've built control loops for nanotech research, DSP accelerators for medical, custom 10 Gb/s sensor for a satellite, video processing, industrial control, and radiation exposure testing.

Here's a common workhorse for designs: a Pipeline FIFO Buffer. Any FIFO depth is allowed, not only powers-of-2. The input-to-output latency is 2 cycles. Can function as a Circular Buffer. The tricky bit in this FIFO design is the read output, which is registered for speed.
fpgacpu.ca/fpga/Pipelin...

I have an open client slot for FPGA design consulting: fpgacpu.ca/gateforge/in...

Over the last 9 years, I've built control loops for nanotech research, DSP accelerators for medical, custom 10 Gb/s sensor for a satellite, video processing, industrial control, and radiation exposure testing.

A Pipeline Half-Buffer: A single pipeline register with ready/valid handshakes. Decouples the input and ouput handshakes (no combinational path), but does not allow concurrent read/write like a full Pipeline Skid Buffer.

fpgacpu.ca/fpga/Pipelin...

Here's the most important pipeline building block: a Skid Buffer. It decouples two sides of a ready/valid handshake to allow back-to-back transfers without a combinational path between input and output, thus fully pipelining the path.

fpgacpu.ca/fpga/Pipelin...

Had to show off for a sec. :) I was amazed when I found that manual at a used book store. So yes, we have examples of Mel's code.

Ah yes. This Mel. :)

This looks like something that would have been possible in the era of delay-line memory. The programming and I/O would have been tricky, but the hardware so minimal and reliable (given vacuum tubes).

I wonder how much of that comes from legacy Verilog-1995 codebases, which is really too limited a language for modern hardware design. (I hold to a subset of the synthesizable subset of Verilog-2001. Modularization takes care of the rest.)

As I struggled today with an FPGA CAD tool's IP code generation and management, it occurred to me that I haven't needed to write HDL-generating code for years now. Extreme modularization, along with generate blocks and parameters, has always sufficed, even for 20k+ line designs.

Bit twiddling hacks are "neat tricks" in software, but they are often branch-free and need no allocated memory, so they map naturally to hardware design.
More listed here: fpgacpu.ca/fpga/reading...

Here is a module which extends the 1-to-N Differential Deserializer by packing two consecutive differential N-bit deserialized words into one differential 2N-bit word and extending the bitslip word-alignment logic to support this double-width word. fpgacpu.ca/fpga/Deseria...

When aligning multiple data channels, you need to pass them through variable-delay shift registers. This is where using an FPGA's built-in shift-register hardware is a must, since using LUTs+FFs ends up being the large majority of the deserializer area!
fpgacpu.ca/fpga/Registe...

A pipeline serial to parallel converter. Reads in multiple serial words and signals when the last input word has been read-in and a new, wider output word is ready to be read-out, in the same cycle if necessary to receive an uninterrupted serial stream.
fpgacpu.ca/fpga/Pipelin...

A deserializer for differential data, with a configurable 1:N ratio, SDR or DDR data rate, and independent positive and negative data polarity input delays and deserializers, which enable bit and word alignment training later on.
fpgacpu.ca/fpga/Deseria...

An IDELAYCTRL instance for calibrating IDELAY2 blocks. This is the first step to high-speed interfaces on Series 7 AMD/Xilinx FPGAs.
fpgacpu.ca/fpga/IDELAYC...

fpgacpu.ca now supports HTTPS! It's still a static site without cookies or Javascript or any inputs, but I was getting reports of problems with browsers, corporate networks, and Google not liking the absence of SSL. Enjoy more easily now!

I have an open slot for a client at this time.
Let's discuss your FPGA design needs!
fpgacpu.ca/gateforge/in...
I'm a consultant doing primarily logic design on FPGAs and related full-stack software development for clients who need application-specific processing for their products.

I have an open slot for a client, starting *immediately*. Let's discuss your FPGA design needs! fpgacpu.ca/gateforge/in...
I'm a consultant doing primarily logic design on FPGAs and related full-stack software development for clients who need application-specific processing for their products.

In one project, I had to first configure an external device before it could generate it's own source-synchronous clock for data and control. This Clock Switchover module detects when the device data clock becomes active and stable and handles clock selection and reset.
fpgacpu.ca/fpga/Clock_S...

I have an open slot for a client, starting in the last week of July. Let's discuss your needs! fpgacpu.ca/gateforge/in...

I'm a consultant doing logic design on FPGAs and related software development (from kernel up to application) for clients who need application-specific processing.

We can now build a saturating accumulator with variable upper/lower limits. I used this as the Integral term of a PID controller, where the limits are dynamically adjusted to limit integral wind-up, which makes the PID controller recover from saturation faster.

fpgacpu.ca/fpga/Accumul...

Here's a Saturating Adder/Subtractor. The limits can be any signed numbers, even dynamically variable. One use is as the final stage of a PID controller, so we can guarantee the output never wraps around and flips sign suddenly, which would be catastrophic.

fpgacpu.ca/fpga/Adder_S...

With an Subtractor that provides the carry-out and the overflow, we can create an Arithmetic Predicates module which computes all possible signed and unsigned comparisons of two numbers. This way we don't have to worry about getting RTL arithmetic right each time.

fpgacpu.ca/fpga/Arithme...

And with those previous modules, we can now build an adder/subtractor module. It's much more complex than usual, but it also gives us all bit carries and the overflow bit, and is independent of Verilog's signed/unsigned arithmetic behaviour.

fpgacpu.ca/fpga/Adder_S...

Next step in getting to saturating arithmetic: a Binary Carry-In calculator, which tells us which bits in a sum had a carry-in, which has many uses (overflow, predicates, vector registers, etc...)

fpgacpu.ca/fpga/CarryIn...

Let's build up to some saturating arithmetic logic. Here's a Width Adjuster, which either extends (optionally signed) or truncates values. I often use it to normalize widths of misc. signals before packing/unpacking/multiplexing/arithmetic/etc...

fpgacpu.ca/fpga/Width_A...

Here's a Pipeline Credit Gate. It let's handshakes complete only if there are available credits, which are added via external pulses and subtracted by each completed handshake. It can ensure that an operation is only considered complete after N items have been read out.
fpgacpu.ca/fpga/Pipelin...

I've updated my "rules for ready/valid handshakes" to describe both a control implementation I made heavy use of in the past year, and to add discussion on the synchronization operation which underlies ready/valid handshakes, much like ready/valid handshakes underlie AXI4.
fpgacpu.ca/fpga/handsha...