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Flux

@willflux.bsky.social

Only hardware makes it possible! FPGA, RISC-V, 68K, OS, graphics, demos, permacomputing http://projectf.io | http://systemtalk.org

249 Followers  |  128 Following  |  185 Posts  |  Joined: 17.11.2024  |  1.6918

Latest posts by willflux.bsky.social on Bluesky

Reading through my posts for the first time in a long time, I noticed a mistake. I claimed the IBM System/360 had a zero register, which isn't true! Thankfully, I was on firmer ground with the CDC 6600 designed by Seymour Cray. πŸ€“

08.08.2025 15:38 β€” πŸ‘ 0    πŸ” 0    πŸ’¬ 0    πŸ“Œ 0
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RISC-V Assembler: Arithmetic This series will help you learn and understand 32-bit RISC-V instructions and programming. The first part looks at load immediate, addition, and subtraction. We’ll also cover sign extension and pseudo...

β€œRISC architecture is going to change everything.”

Have you seen my seven-part Guide to #riscv assembler? No ads or crappy popups. projectf.io/posts/riscv-...

08.08.2025 14:45 β€” πŸ‘ 5    πŸ” 2    πŸ’¬ 1    πŸ“Œ 0
Photograph of Icepi Zero dev board from Crowd Supply website showing components, including Lattice FPGA, SDRAM, and connectors.

Photograph of Icepi Zero dev board from Crowd Supply website showing components, including Lattice FPGA, SDRAM, and connectors.

Icepi Zero looks like an interesting open-source ECP5 #FPGA dev board. It’s got a decent spec in a small form factor. The only obvious omission is audio out. The big question is, how much will it cost? www.crowdsupply.com/icy-electron...

05.08.2025 20:21 β€” πŸ‘ 6    πŸ” 0    πŸ’¬ 0    πŸ“Œ 0

I'm disappointed you've not posted any updates on the day of #StormFloris.

04.08.2025 11:40 β€” πŸ‘ 0    πŸ” 0    πŸ’¬ 0    πŸ“Œ 0
Verilator LibSDL simulation running on macOS showing a simple white square on a navy blue background.

Verilator LibSDL simulation running on macOS showing a simple white square on a navy blue background.

ULX3S FPGA dev board connected to LCD monitor showing hitomezashi stitch pattern in bright yellow on a blue background.

ULX3S FPGA dev board connected to LCD monitor showing hitomezashi stitch pattern in bright yellow on a blue background.

I don't yet have a complete system to share with you. Getting the design right takes a lot of experimentation; I've hit dead ends several times. I'll gradually introduce components over the coming months. The first part looks at display signals. #FPGA πŸ“Ί projectf.io/isle/display...

04.08.2025 09:53 β€” πŸ‘ 4    πŸ” 0    πŸ’¬ 0    πŸ“Œ 0
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GitHub - projf/isle: Isle FPGA Computer Isle FPGA Computer. Contribute to projf/isle development by creating an account on GitHub.

Isle targets Machdyne Lakritz, @digilent.bsky.social Nexys Video, Radiona ULX3S, and Verilator/SDL simulation that runs on your PC or Mac.

Designs, docs, and test benches are available under the MIT license: github.com/projf/isle

04.08.2025 08:25 β€” πŸ‘ 4    πŸ” 0    πŸ’¬ 1    πŸ“Œ 0
HAL 7 Minutes before the doors close

HAL 7 Minutes before the doors close

β€œNo 9000 computer has ever made a mistake or distorted information.”

03.08.2025 20:33 β€” πŸ‘ 1    πŸ” 0    πŸ’¬ 0    πŸ“Œ 0

Thank you! πŸ™

01.08.2025 13:11 β€” πŸ‘ 0    πŸ” 0    πŸ’¬ 0    πŸ“Œ 0
A coconut sapling on a tropical beach.

A coconut sapling on a tropical beach.

Isle 🏝️ is my new #FPGA project.

Isle is a simple, modern computer β€” an open design that encourages tinkering, experimentation, and doing your own thing. I hope to inspire you to come on a journey with me and build your own computer. projectf.io/isle/fpga-co...

01.08.2025 08:14 β€” πŸ‘ 15    πŸ” 5    πŸ’¬ 2    πŸ“Œ 0

The wels (catfish) is a fine choice for the cover πŸ˜†

31.07.2025 07:29 β€” πŸ‘ 1    πŸ” 0    πŸ’¬ 0    πŸ“Œ 0
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In honor of the upcoming ICLAD conference, here’s a gem from one of the first LLM-for-hardware-design panels that was at ICCAD. How far we have come.

16.06.2025 22:53 β€” πŸ‘ 6    πŸ” 2    πŸ’¬ 1    πŸ“Œ 0

Here are a few of my own suggestions:

@khubbard.bsky.social - wrote the best intro to FPGAs
@gmahovlic.bsky.social - designing brilliant FPGA boards
@rascalfoxfire.bsky.social - building a 16-bit RISC CPU
@lockfarm.bsky.social - maker of 8-bit Z80 beasts
@tomverbeure.bsky.social - plays with FPGAs

30.07.2025 16:42 β€” πŸ‘ 10    πŸ” 0    πŸ’¬ 1    πŸ“Œ 2

I love to hear about interesting accounts to follow for #FPGA, #riscv, #oshw, and #permacomputing. πŸ’›

30.07.2025 15:41 β€” πŸ‘ 3    πŸ” 1    πŸ’¬ 1    πŸ“Œ 0
FPGA dev board connected to LCD panel showing the text "FLUX FPGA EARTHRISE" in an angular typeface.

FPGA dev board connected to LCD panel showing the text "FLUX FPGA EARTHRISE" in an angular typeface.

New #FPGA project from me this Friday. Just been validating the HTML and running some final tests. I thought it was time I nailed my colours to the mast. πŸš€

30.07.2025 10:02 β€” πŸ‘ 3    πŸ” 0    πŸ’¬ 0    πŸ“Œ 0
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RP2350 A4, RP2354, and a new Hacking Challenge - Raspberry Pi New A4 stepping of our RP2350 microcontroller now available, with security and other improvements. Plus: another RP2350 Hacking Challenge!

New RP2350 stepping just dropped, E9 fixed.

www.raspberrypi.com/news/rp2350-...

29.07.2025 13:29 β€” πŸ‘ 106    πŸ” 23    πŸ’¬ 4    πŸ“Œ 5

β€œWord (computer architecture)” on Wikipedia is surprisingly interesting. The influence of System/360 is evident again. The big table of word sizes is engrossing. The Manchester Baby had 32-bit words in 1948, though it only had 32 of them. πŸ€” en.wikipedia.org/wiki/Word_(c...

28.07.2025 08:48 β€” πŸ‘ 2    πŸ” 1    πŸ’¬ 0    πŸ“Œ 0

Apply hedgehogs for immediate relief. πŸ¦”

26.07.2025 21:34 β€” πŸ‘ 1    πŸ” 0    πŸ’¬ 0    πŸ“Œ 0

Be not afeard; the isle is full of noises,
Sounds, and sweet airs, that give delight and hurt not. 🏝️

26.07.2025 10:49 β€” πŸ‘ 0    πŸ” 0    πŸ’¬ 1    πŸ“Œ 0
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Want to help build a crowdsourced microcontroller?

You're invited to design peripherals (UARTs, timers, synths, etc.) for a @riscv.org.web.brid.gy chip that will be fabbed for real!

Take part for free!

tinytapeout.com/competitions...

25.07.2025 10:57 β€” πŸ‘ 55    πŸ” 34    πŸ’¬ 2    πŸ“Œ 3
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As I did not post for a long time I will start from an end. We got #ULX5M-GS up and running!!! #CM5 pin compatible #FPGA #SoM with #EU Cologne #GateMate A1 and fully open source toolchain. Still lots of work left, but I am really happy to see DVI out!

21.07.2025 22:45 β€” πŸ‘ 5    πŸ” 2    πŸ’¬ 0    πŸ“Œ 0
macOS Terminal showing ps output for "/opt/oss-cad-suite-2025-01-30/libexec/dot -Txdot" with 1507:42.41 minutes of CPU time.

macOS Terminal showing ps output for "/opt/oss-cad-suite-2025-01-30/libexec/dot -Txdot" with 1507:42.41 minutes of CPU time.

My MacBook Air battery life has sucked recently, and it occurred to me to check if I'd left a Verilator simulation running. Instead, I found dot(1) with over 1500 minutes of CPU time!

MOAR DoTs! πŸ˜‰

25.07.2025 10:06 β€” πŸ‘ 3    πŸ” 0    πŸ’¬ 0    πŸ“Œ 0
Front cover of Byte August 1985 showing an Amiga 1000 displaying artwork.

Front cover of Byte August 1985 showing an Amiga 1000 displaying artwork.

"We think this machine will be a great success: if that happens the #Amiga will probably have a great effect on other personal computer companies and the industry in general." β€” Byte August 1985

23.07.2025 14:02 β€” πŸ‘ 4    πŸ” 2    πŸ’¬ 0    πŸ“Œ 0

# I pictured a rainbow
# You held it in your hands

20.07.2025 17:52 β€” πŸ‘ 1    πŸ” 0    πŸ’¬ 0    πŸ“Œ 0

Block ram (bram) is one of the best FPGA features. Bram lets me create a 32-bit vram with a 1-bit write mask. You write 32 bits at a time *and* control individual pixels, even with 1, 2, and 4-bit graphics. No need for the graphics engine to read, mask, then write. Simple and fast.

15.07.2025 19:43 β€” πŸ‘ 3    πŸ” 0    πŸ’¬ 0    πŸ“Œ 0
Herring gull staring through a window.

Herring gull staring through a window.

You really know dinosaurs didn’t go extinct when they look you in the eye through the kitchen window. πŸ¦•

15.07.2025 18:00 β€” πŸ‘ 2    πŸ” 0    πŸ’¬ 0    πŸ“Œ 0
ULX3S FPGA dev board connected to USB and HDMI cables. In the background a colourful image of purple and white crocuses on a computer monitor.

ULX3S FPGA dev board connected to USB and HDMI cables. In the background a colourful image of purple and white crocuses on a computer monitor.

We've tested 2, 4, and 16 colours, so why not 256? All colour depths supported by the 32-bit bram design with bit (sic) write. 32 x ECP5 brams is 64 KiB, which fits nicely in 25F+. Shown here with ULX3S #FPGA dev board.

15.07.2025 14:49 β€” πŸ‘ 6    πŸ” 0    πŸ’¬ 1    πŸ“Œ 0

George at BBC Education did, but mostly no. You might also remember Wayne’s profanity filter called Merde and accessibility tool called Betsie.

12.07.2025 08:36 β€” πŸ‘ 1    πŸ” 0    πŸ’¬ 1    πŸ“Œ 0

Haha. I remember developing the frontend for Wayne’s Gigaquiz so there was a friendly web interface for creating quizzes. The education quizzes were popular, but your 100 question Cult quizzes were almost the most popular thing on bbc.co.uk I think.

12.07.2025 08:28 β€” πŸ‘ 1    πŸ” 0    πŸ’¬ 1    πŸ“Œ 0

I think i got something in the 16 bit RISC ISA department. I only need to finish designing the MMU control register signals. It is also my first ISA supporting (half precision) floats so i can finally start doing 3D stuff. Currently on a first Logisim implementation before going to Verilog

11.07.2025 00:11 β€” πŸ‘ 3    πŸ” 1    πŸ’¬ 1    πŸ“Œ 0

8 hours to Skye by bus. Β£121 sounds steep to me.

10.07.2025 14:56 β€” πŸ‘ 1    πŸ” 0    πŸ’¬ 1    πŸ“Œ 0

@willflux is following 20 prominent accounts