Rohan makes ASICs 🛠️

Fly through video for ROM-less Cordic Engine design.

This design is on TTSKY25A shuttle by @tinytapeout.com

Made easy with BlenderGDS plugin - github.com/aesc-silicon...

@mattvenn.net @urishaked.bsky.social @aksharvastarpara.bsky.social

Fly through video for ROM-less Cordic Engine design.

This design is on TTSKY25A shuttle by @tinytapeout.com

Made easy with BlenderGDS plugin - github.com/aesc-silicon...

@mattvenn.net @urishaked.bsky.social @aksharvastarpara.bsky.social

How well do SP10 probes perform when used with high-frequency oscilloscope measurements?

welcome to our cordic city!!

welcome to our cordic city!!

yes! it's from that same blender plugin.

Yes, that’s a GDSII render.
Yes, it’s inside Blender.
Yes, it’s our design on TTSKY25A chip.
@tinytapeout.com @mattvenn.net @urishaked.bsky.social

oh! got it.

can you post the "GPU running on FPGA"?

....while CSIS sponsers terrorism on Indian soil.

Innovation in ZMOS process node led to development of modern CMOS and BiCMOS process node where we have 20 metal layers.

For instance, Sky130A 130nm process node have upto 5 metal layers.
bsky.app/profile/roha...

Back in the day, NMOS chips used only one metal layer, so designers had to squeeze all the wiring onto a single surface.

Metal 1: used for local interconnects, this allowed short and dense wiring.

Metal 2: used for global signals like buses, clocks, power.

This is the DCJ11 PDP-11 processor, built using the old-school ZMOS tech, a 3  μm NMOS process with two interconnect layers.

It was one of the first NMOS processes to use separate metal layers for local connections and global signals.

🤩🤩

Another mike bell project to fab!

Fomu fpga?

chinese semiconductor industry is creative for sure.

Nice idea for analog tapeout for some day.

This looks like a matrix.
Each one has 128 analog switches.
We can do 8x16 analog array with one.

So this is actually a analog matrix.

And guess what whole hdl for this is written in both system verilog and chisel/scala.

Note that Zve32x extension works only on integers, it needs Zicsr and Zvl32b base profiles to be implemented first.

Although the element size is capped at 32 bits, the wide vector registers (256 bits) still allow multiple elements to be processed simultaneously.

Google has open sourced its Coral NPU, which uses a 32 bit RISC V core with the Zve32x extension. It supports vector arithmetic on data ≤ 32 bits, making it great for DSP applications.

It has been prototyped on a Xilinx Ultrascale Plus FPGA platform.

github.com/google-coral...

YouTube video by Crowd Supply Teardown Session 56: wafer.space with Tim Ansell

Leo Moser and myself will be on @crowdsupply.bsky.social 's Teardown Session talking with @helenleigh.bsky.social about
@wafer.space this Thursday (3rd October) - youtu.be/tEOmnN8IAjs

this ryt? ku-fpg.github.io/software/kan...

I'll try this. It's more mature I guess?

We already have chisel for this right? or it lacks on something that only Haskell can provide?

FYI : Original electronic diary was invented by a Indian guy known as Satyan Pitroda, alias Sam Pitroda.

He may be a tad racist, but a great guy. I mean all Indians are racist to each other, who cares.

www.computerhistory.org/revolution/m...

It was awesome to be on @chrisgammell.bsky.social 's Amp Hour podcast again. Find out more about my latest endeavor to make custom silicon manufacturing accessible and follow @wafer.space and bookmark wafer.space to keep up to date!

It can be powered directly from a Pi USB port
with 60% brightness. It needs a external supply for 100% brightness.

it's ROM generated from ROM compiler.

*This is the one for storing TV codes for that IR LED project

*and not the atari one

259 Zilog Z80 - Tiny Tapeout Z80 open-source silicon. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.

There is one Open Z80 implementation by @renaldas.bsky.social on TT07.

www.tinytapeout.com/chips/tt07/t...

yeah, openroad STA gives you a rough estimate for power.

It's a static power estimation obviously. Also it's a digital tapeout, so I don't expect it to be a very power hungry design (assuming SKY130A cells are optimized).

Low power math within few clock cycles.

Imagine it, then put it into silicon.

Made by Vicharak aka @aksharvastarpara.bsky.social 's team and two FPGA freaks.

Check - t.co/vBGGA2i0uX

Thanks @mattvenn.net and @urishaked.bsky.social and whole @tinytapeout.com team for making this possible.