Board manufacturer date of wk10 2024. Wild that this issue is still making it into designs.
28.09.2025 23:08 โ ๐ 2 ๐ 0 ๐ฌ 0 ๐ 0@gregdavill.bsky.social
ASIC/FPGA/PCB/FW engineer at ASTC ๐งโโ๏ธ (He/Him) I also take macro photos of electronics
Board manufacturer date of wk10 2024. Wild that this issue is still making it into designs.
28.09.2025 23:08 โ ๐ 2 ๐ 0 ๐ฌ 0 ๐ 0Circuit board with bodge wire neatly snaking between passives. Connecting two vias.
Terminal output from nextpnr showing an error that T16 is not available on this package.
nextpnr output showing device usage around 15% of the logic for a HS USB core and QSPI logic to implement a boot loader.
I'd forgotten that the ECP5-25F doesn't have all the I/O, and 4 or so pins that are on the 45/85F are N/C on the 25F. I just happened to use one of these for the ULPI interface. ๐ฅฒ
Bodge wire to the rescue! Now we're enumerating again!
USB boot loader in gateware, takes up ~15% of the device
If by fab house, you mean my a toaster oven in my fabulous houses garage? Then yes. ๐
01.09.2025 22:41 โ ๐ 6 ๐ 0 ๐ฌ 0 ๐ 0Assembled circuit board with soldering defect. A tombstoned part. In which a 2 terminal passive is only soldered to one side so it raises up like a tombstone. A small yellow sticker with an arrow points at the defect on the board.
Tombstone time
01.09.2025 22:34 โ ๐ 12 ๐ 0 ๐ฌ 2 ๐ 0Small update to PCB and I forgot to buy a new stencil ๐
01.09.2025 22:09 โ ๐ 2 ๐ 0 ๐ฌ 0 ๐ 0Circuit board with a large BGA footprint. Some pads on the BGA package are larger than others.
Circuit board with a large BGA footprint. All the pads on the BGA package are the same size.
These two boards have the same BGA geometry defined in their gerbers. For some reason JLCs DFM adjustments have expanded all the "via in pad" connections.
Makes for an interesting visual effect.
Circuit board with solder paste applied. The photo is close enough so you can just start to make out the tiny spheres that make up solder paste. There are 2 components which don't have solder paste applied.
Circuit board with solder paste applied. The photo is close enough so you can just start to make out the tiny spheres that make up solder paste. There are 2 components which don't have solder paste applied.
How's my solder paste application?
I think I missed some spots. ๐ซฃ
When I started using brand name AMTECH flux. I realised it had a โsweetโ smell, then immediately bought a fume extractor, because I realised if I was smelling that I was 100% inhaling the rosin and additive vapours ๐จ๐ตโ๐ซ
01.09.2025 01:46 โ ๐ 2 ๐ 0 ๐ฌ 0 ๐ 0ECPBreaker FPGA development board featuring a Lattice ECP5 FGPA. Being programmed via JTAG from an ORBTrace, that is powered by a Lattice ECP5.
FPGAs programming FPGAs ๐ข
23.08.2025 02:53 โ ๐ 20 ๐ 1 ๐ฌ 0 ๐ 0Saleae trace with QSPI signals shown
The bodge works!
A DFF in front of the ECP5's FPGA SPI configuration port before a mix leading to FLASH and PSRAM. Enabling an initial jump through FLASH where the clock frequency is bumped and QSPI entered.
This now fixes an issue violating the PSRAM's tCE<8us requirement.
Iโve noticed looking at some modern SMD 32k quartz crystals may have what look like laser trim dots on the forks. Could that be one reason to manufacture these with a glass top rather than metal?
17.08.2025 04:39 โ ๐ 3 ๐ 0 ๐ฌ 1 ๐ 0PCB layout in KiCad showing a bodge plan
Circuit board with bodge wires connecting a new component
Plan vs. Execution
The messier the plan the cleaner the bodge looks in comparison. ๐
Nicely done! Looks similar to the XPS I did the same mod to. Resistor straps to inform BIOS of larger DRAM parts. Luckily I got a board-view which shower the net names. Made it easy to work out the 16GB variant.
15.08.2025 05:01 โ ๐ 5 ๐ 0 ๐ฌ 0 ๐ 0USB-C with cable cut, showing only 3 wires: red, black and white.
USB-C with cable cut, showing only 3 wires: red, black and white.
Can't recall where this came from, but ended up in my labs cable drawer. Curious why it wouldn't enumerate.. ๐คฎ
14.08.2025 06:36 โ ๐ 9 ๐ 0 ๐ฌ 2 ๐ 0Electrical schematic showing pin ordering into a connector. Next to the PCB layout which has silkscreen that in no way matches.
Why is my circuit board lying to me ๐ฅฒ
03.08.2025 07:57 โ ๐ 6 ๐ 0 ๐ฌ 1 ๐ 0โIโd rather write the hwโ much easier ๐๐๐คฃ
26.07.2025 02:24 โ ๐ 2 ๐ 0 ๐ฌ 0 ๐ 0Impedance control is a myth. A term made by big circuit to sell more ground planes. /s
27.06.2025 23:26 โ ๐ 7 ๐ 0 ๐ฌ 0 ๐ 0Smoke test passed! ๐ฅ
Voltages all look good
Circuit board propped up on a mechanical pencil
Circuit board in-front of a red coffee mug
Circuit board in-front of a red coffee mug
๐ Freshly assembled, still not sure if the design even works ๐ซฃ
24.06.2025 03:45 โ ๐ 23 ๐ 0 ๐ฌ 1 ๐ 0Assembly view of circuit board showing every decoupling capacitor highlighted
Decoupling? Yes. โ
12.06.2025 09:21 โ ๐ 10 ๐ 0 ๐ฌ 2 ๐ 0Circuit board with solder paste applied
Circuit board with solder paste applied
Circuit board with solder paste applied
Circuit board with solder paste applied
A nice solder paste application ๐ซ
12.06.2025 09:13 โ ๐ 12 ๐ 0 ๐ฌ 1 ๐ 0Circuit boards alongside a 3d printed enclosure, solder paste stencil and some tools.
Circuit board macro photo
Circuit board macro photo
Circuit boards are in! ๐
12.06.2025 01:42 โ ๐ 23 ๐ 1 ๐ฌ 1 ๐ 0CAD view of an enclosure designed around a circuit board
Designed a quick and simple 3d printed case
02.06.2025 22:40 โ ๐ 14 ๐ 0 ๐ฌ 1 ๐ 0Unfortunately not, this is actually an old ButterStick r0.2
31.05.2025 01:59 โ ๐ 1 ๐ 0 ๐ฌ 0 ๐ 0I've been using KiCad 9's new table features to aid in schematic documentation.
I guess it makes sense.. But still puzzled me for a moment that you can perform a vertical/horizontal mirror on a single cell. ๐
3d CAD showing a fillet inside a corner of a part, the geometry is using native rounded surfaces, and looks clean.
Much better ๐
10.05.2025 06:35 โ ๐ 4 ๐ 0 ๐ฌ 0 ๐ 0View from 3d CAD, showing a rounded corner of an object, except it's not actually round, rather lot of straight lines.
Glad I can jump back in the timeline. Found the culprit!
Top object is an imported PCB, arcs on the board outline get converted to straight-line segments when it's exported from KiCad.
The purple lines are projected from this PCB outline. Then I've applied an offset to account for tolerance.
3d CAD showing a rounded surface, that is made up small flat planes, rather than a continuous arc. A fillet has created awkward joins to these flat planes.
Whoops, it's quick and easy to simply base 3d geometry off a KiCad board outline. But the topology has caught up to me. ๐ซ
10.05.2025 06:13 โ ๐ 4 ๐ 0 ๐ฌ 1 ๐ 0Hand holding a circuit board with diffusion pattern
Designed this board years ago, and finally ordered it. The pattern looks really cool on the physical boards.
github.com/gregdavill/a...