PipelineC

"How do FPGAs execute blocking assignments in one clock cycle?"

Is the perfect question to frame common learning curve hurdles that folks need to get over when learning HDL.

www.reddit.com/r/FPGA/comme...

#fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

From the FPGA community on Reddit: How to send a struct from one dev board to another? Explore this post and more from the FPGA community

How to send a struct from one dev board to another? A PipelineC Story

#hdl #hls #RTL #fpga #ethernet #i2s #hardware

www.reddit.com/r/FPGA/comme...

implemented a xilinx virtual cable applet. this way you can connect vivado to glasgow and program any supported FPGA

glasgow-embedded.org/latest/apple...

Heh not there yet 🤪

Leave it to awesome folks like this guy 😏 www.furygpu.com

Yes that python running hardware has been all over this morning - super cool! Reminds me of some java/lisp machines from back in the day!

Also saw this Python to Digital Logic work today too - reminds me a smidge of pipelinec 🤓 repository.lincoln.ac.uk/articles/con...

Oh wow I didnt recall us speaking - but your post did remind me of that old desire for posix in hardware of some kind 🤓 Good to hear you are still around looking at cool things too!

#FPGA Congrats to Prof. Jason Cong, for Chuck Thacker Breakthrough in Computing Award, recognized for "fundamental contributions to the design and automation of field-programmable systems and customizable computing".

insidehpc.com/2025/04/jaso...

C-to-gates was a dream until Cong made it real.

Check out @dutracgi@mastodon.radio 's very cool #16APSK #FPGA Modulator written in #PipelineC #HDL !
#dsp #sdr #rf #apsk #dac #deltasigma #space #qam #radio #hardware www.linkedin.com/pulse/16-aps...

Will this (fpga+cpu+graphics) make it into a projectf tutorial somewhere? Seems like everyone wants to make their own GPU and this feels like a perfect intro 🤓

yeah 'set the clock too high' build to evaluate fmax is something the pipelinec tool does as well. But be careful some tools, if given a large design with a goal too high they will give up early and you won't get representative fmax out.

Id say its this reasoning that the tools don't tell you fmax. Most users have a target and just want to know if they made it there or not 🤷

It's a C like HDL. So gets you into describing hardware without needing to learn verilog sensitivity lists and blocking non blocking etc. So just hopefully easier. And then has some fancier compiler things it can do: ex. help you pipeline for high performance designs 🤙

Happen to know some basic C? If you are in the mood to experiment with getting right to hardware design and past the annoying Verilog/VHDL learning curve - happy to chat about PipelineC 🤓

capture of last 4 bytes of ethernet frame shown in gtkwave

What can you do with reading arbitrary #FPGA registers out of your design over #UART? Capture time series data (last four #ethernet packet bytes), write a little #python script that launches #GTKWave, and you have a tiny homemade cross platform logic analyzer thing!
github.com/JulianKemmer...

How does the hardware work? Probes can be in any clock domain and cdc to UART clock is handled for you with small FIFOs. Host PC control program read enable pulse causes hardware to respond over UART with the sample bytes from your debug probe. All included as a pipelinec library.

struct ddef and print func code

How do you configure this? You define a type and a method for printing the data to console. The struct type is shared between software C and hardware PipelineC. Upon receiving bytes for your probe they are converted to your struct type and printed as specified.

print of mac address matching wireshark

From there the bytes of probe data are shipped over UART to a host PC. A simple C program reading UART bytes displays your data:

declaring and assigning debug probes code

#hardware debugging and wanted to see some #ethernet MAC address registers down in my pico-ice #ice40 #fpga design. Don't want manufacturer specific ILAs. Don't want to route signals to top, external #debug equipment I don't have.

Just assign to #UART debug probe wire:
github.com/JulianKemmer...

Not having #AMD #Xilinx #Vivado #Chipscope based live #hardware debug for the #picoice #Lattice #ice40 #FPGA was a little annoying

so I have revived the small pipelinec project that was sorta a build your own chipscope attempt 🤙 and will demo that on the pico ice

Yay those cheap #hardware #ethernet phy #pmod -LIKE things work with the pico-ice #ice40 #FPGA . Thanks for your help with RMII interface @dutracgi@mastodon.radio! #embedded #HDL #RTL #Verilog #VHDL #HLS github.com/JulianKemmer...

👋 Hi, I’m Max! Principal Engineer @ Intel & lead of ROHD, an open-source project making hardware design more fun & accessible.

Passionate about hardware, software, open source, and Dart. Also snowboarding, gaming, & new tech!

#introduction #opensource #hardware #FPGA #SoC #Dart #HDL #ROHD

I taped out a variety of adders on open source silicon and Kogge-Stone adders were the fastest for all widths above 8 bits.

Yosys now has plugins to choose which topology you want! Read more here: www.zerotoasiccourse.com/post/instrum...

YouTube video by PipelineC Introduction to PipelineC

Learn PipelineC #HDL basics featuring the pico-ice dev board from tinyVision.ai! It has a Lattice Semiconductor @latticesemi #ice40 #FPGA and @Raspberrypi. This intro covers #LED, #UART, and #VGA projects using OSS CAD Suite tools. #hardware #RTL #Verilog #VHDL #HLS
www.youtube.com/watch?v=wWdv...

Don't forget the intro to pipelinec talk is just over 24 hours away! See you there folks 🤓
#HDL #ice40 #fpga #RaspberryPi #hardware #RTL #Verilog #VHDL #HLS

Let's meet on Watch2Gether Watch2Gether lets you watch videos with your friends, synchronized at the same time.

Saturday Jan. 18th
12PM EST
via Watch2Gether:
w2g.tv/?r=tx4wy991roihexnj7g
(no account required)

Recording published after.

github.com/JulianKemmerer/PipelineC/wiki
pico-ice.tinyvision.ai
github.com/YosysHQ/oss-cad-suite-build

Fallback location is tinyVision.ai Discord: discord.gg/zzZZj57ZmZ

Come learn some PipelineC #HDL basics featuring the pico-ice dev board from tinyVision.ai! It has a Lattice Semiconductor @latticesemi #ice40 #FPGA and @raspberrypi.com. This intro talk will cover #LED, #UART, and #VGA projects using OSS CAD Suite tools. #hardware #RTL #Verilog #VHDL #HLS

Nice! Looking good 🤓

I like to take advantage of how 'C' can describe both software or custom hardware architectures 😏 #PipelineC . Sometimes you can even use the same code for a software renderer and hardware pipeline! And so many people know C, lets get them doing fun FPGA stuff!

In the mood for the littlest bit of #FPGA #GameDev? 🤓 Check out this pico-ice based pong demo. Just need #VGA #pmod and #UART connected to host PC. #HDL #hardware #RTL #Verilog #VHDL #HLS #lattice #ice40 github.com/JulianKemmer...

Dev Board Setup A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature. - JulianKemmerer/PipelineC

Gifted a new #FPGA dev board this season? 🤓 PipelineC aims to make #hardware description easier for #embedded folks.
Check out the new getting start page. Happy to help you get going! #hdl #verilog #vhdl #hls
github.com/JulianKemmer...

Part of why FPGAs are amazing is getting to be part of this hard 💪 hardware world while getting a relatively faster recompile and test cycle like software. I♥️#FPGA