PipelineC

shared resource bus diagram

Existing libraries help: memory mapping is as simple as a struct. All stitched together with valid ready handshaking 'streams'. Writes done over StreamSoC's AXI-Lite like 'shared resource bus' that comes with helper FSMs

github.com/JulianKemmer...

#hardware #fpga #rtl #hls #hdl #graphics #gpu #cpu

Easy: draw_rect_t struct shared between embedded C software and PipelineC hardware. Mem mapped registers enqueue into command FIFO. Small hardware FSM reads from cmd FIFO does simple iteration to draw a rect of pixels.

github.com/JulianKemmer...

#hardware #fpga #rtl #hls #hdl #graphics #gpu #cpu

streamsoc new 2d drawing block

Is a hardware FSM that draws rectangles to a frame buffer a GPU? Well whatever you call it, it's no longer the CPU pushing pixels in the PipelineC StreamSoC design. Now it sends 'draw rectangle' commands to hardware. And how? #hardware #fpga #rtl #hls #hdl #graphics #gpu #cpu

Results from the Advent of FPGA Challenge At the end of last year, we decided to try something new: achallenge that would runalongside Advent of Code, where we asked the community toshow us how they ...

Make sure to see all the other neat Advent of FPGA solutions that Jane Street highlighted too!

blog.janestreet.com/advent-of-fp...

aof banner

Check out PipelineC #HDL Advent of FPGA #hardware solutions: high perf, deeply pipelined, multiple #FPGA platforms, 10's Gbit per sec throughput, easily scales: variable latency off chip mem, faster off chip IO and more resources.

github.com/JulianKemmer...

#rtl #hls #verilog #vhdl #asic #eda

Advent of Code Day 5: Iterates over RAM holding fresh ID ranges. Autopipeline checks N IDs against M ranges each cycle. Easily does N=3,M=2 at ~235MHz, ~1.4 billion ID-in-range checks computed per sec 😎

github.com/JulianKemmer...

#aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎

github.com/JulianKemmer...

#aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

Advent of Code Day 4: video-like stream of 'pixel' data to a sliding 3x3 window via line buffer fifos. Auto pipeline for kernel function (counting neighbors), ~150M windows per sec. github.com/JulianKemmer...

#fpga #rtl #hdl #hls #aoc25

Advent of Code Day 9: Iterates over RAM holding points. Autopipeline computes N rectangle areas per clock cycle and finds max. Easily does N=4 at ~100MHz with few pipeline stages, ~400M rect areas computed per sec 🎄

github.com/JulianKemmer...

#fpga #rtl #hdl #hls #aoc25

Advent of Code Day 3 pipelined no back pressure. N ascii chars as input each cycle. finding max pair of digits pipelined arbitrarily. 8 chars of input each cycle? no problem to get FMAX of 100+MHz.

~1 Gbyte per sec of ascii could be processed 😎 🎄
github.com/JulianKemmer... #aoc25 #fpga #hdl #hls

Advent of Code 2025 Day 2 in FPGA 🤓

github.com/JulianKemmer...

#fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

"How do FPGAs execute blocking assignments in one clock cycle?"

Is the perfect question to frame common learning curve hurdles that folks need to get over when learning HDL.

www.reddit.com/r/FPGA/comme...

#fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

From the FPGA community on Reddit: How to send a struct from one dev board to another? Explore this post and more from the FPGA community

How to send a struct from one dev board to another? A PipelineC Story

#hdl #hls #RTL #fpga #ethernet #i2s #hardware

www.reddit.com/r/FPGA/comme...

implemented a xilinx virtual cable applet. this way you can connect vivado to glasgow and program any supported FPGA

glasgow-embedded.org/latest/apple...

Heh not there yet 🤪

Leave it to awesome folks like this guy 😏 www.furygpu.com

Yes that python running hardware has been all over this morning - super cool! Reminds me of some java/lisp machines from back in the day!

Also saw this Python to Digital Logic work today too - reminds me a smidge of pipelinec 🤓 repository.lincoln.ac.uk/articles/con...

Oh wow I didnt recall us speaking - but your post did remind me of that old desire for posix in hardware of some kind 🤓 Good to hear you are still around looking at cool things too!

#FPGA Congrats to Prof. Jason Cong, for Chuck Thacker Breakthrough in Computing Award, recognized for "fundamental contributions to the design and automation of field-programmable systems and customizable computing".

insidehpc.com/2025/04/jaso...

C-to-gates was a dream until Cong made it real.

Check out @dutracgi@mastodon.radio 's very cool #16APSK #FPGA Modulator written in #PipelineC #HDL !
#dsp #sdr #rf #apsk #dac #deltasigma #space #qam #radio #hardware www.linkedin.com/pulse/16-aps...

Will this (fpga+cpu+graphics) make it into a projectf tutorial somewhere? Seems like everyone wants to make their own GPU and this feels like a perfect intro 🤓

yeah 'set the clock too high' build to evaluate fmax is something the pipelinec tool does as well. But be careful some tools, if given a large design with a goal too high they will give up early and you won't get representative fmax out.

Id say its this reasoning that the tools don't tell you fmax. Most users have a target and just want to know if they made it there or not 🤷

It's a C like HDL. So gets you into describing hardware without needing to learn verilog sensitivity lists and blocking non blocking etc. So just hopefully easier. And then has some fancier compiler things it can do: ex. help you pipeline for high performance designs 🤙

Happen to know some basic C? If you are in the mood to experiment with getting right to hardware design and past the annoying Verilog/VHDL learning curve - happy to chat about PipelineC 🤓

capture of last 4 bytes of ethernet frame shown in gtkwave

What can you do with reading arbitrary #FPGA registers out of your design over #UART? Capture time series data (last four #ethernet packet bytes), write a little #python script that launches #GTKWave, and you have a tiny homemade cross platform logic analyzer thing!
github.com/JulianKemmer...

How does the hardware work? Probes can be in any clock domain and cdc to UART clock is handled for you with small FIFOs. Host PC control program read enable pulse causes hardware to respond over UART with the sample bytes from your debug probe. All included as a pipelinec library.

struct ddef and print func code

How do you configure this? You define a type and a method for printing the data to console. The struct type is shared between software C and hardware PipelineC. Upon receiving bytes for your probe they are converted to your struct type and printed as specified.

print of mac address matching wireshark

From there the bytes of probe data are shipped over UART to a host PC. A simple C program reading UART bytes displays your data:

declaring and assigning debug probes code

#hardware debugging and wanted to see some #ethernet MAC address registers down in my pico-ice #ice40 #fpga design. Don't want manufacturer specific ILAs. Don't want to route signals to top, external #debug equipment I don't have.

Just assign to #UART debug probe wire:
github.com/JulianKemmer...

Not having #AMD #Xilinx #Vivado #Chipscope based live #hardware debug for the #picoice #Lattice #ice40 #FPGA was a little annoying

so I have revived the small pipelinec project that was sorta a build your own chipscope attempt 🤙 and will demo that on the pico ice