DashRTL v2025.12 is now available for free trial:
dashthru.com/freetrial
#SystemVerilog #RTL #VLSI
08.01.2026 09:59 โ ๐ 0 ๐ 0 ๐ฌ 0 ๐ 0
SV RTL may compile in sim/lint but fail later in synthesis, LEC, or FPGA tools. 10 examples from SV12 LRM are tested, yet tool support is inconsistent.
Full list ๐ github.com/DashThru/SV_...
DashRTL will have full SV 2023 LRM syntax coverage, to flag any syntax that may cause cross-tool issues.
15.09.2025 08:58 โ ๐ 0 ๐ 0 ๐ฌ 0 ๐ 0
That was like 20 years ago. You must be a VLSI veteran.
25.08.2025 04:03 โ ๐ 1 ๐ 0 ๐ฌ 0 ๐ 0
Combine Tcl and Python in a single EDA Shell: tclpysh playground is now online.
dashthru.com/playground
13.08.2025 07:03 โ ๐ 1 ๐ 0 ๐ฌ 0 ๐ 0
EDA tool runtime too long? DashRTL is the ONLY solution that accelerates RTL analyze and elaborate with MULTI-CORE processing.
#VLSI #SystemVerilog #Verilog #RTL #HDL
11.08.2025 08:31 โ ๐ 3 ๐ 0 ๐ฌ 0 ๐ 0
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Python / C++ / VHDL / SystemVerilog / ๆ้ฉๅ็่ซ / ๆฐ็ๆ้ฉๅ / ๆ้ฉ่จญ่จ / ็ซถ้ฆฌ / Typst
Prisoner to discrepancies in SystemVerilog feature support | ๐@sylvie | pfp by @sylvie
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Professional FPGA developer, mostly in SystemVerilog. I also write Python, MATLAB and C code. I'm interested in the state of this industry.
Creator and maintainer of Verilog-HDL/SystemVerilog for VS Code extension. Machine learning compiler researcher, contributor to Apache TVM/Hummingbird, rock climbing enthusiast.
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Electrical engineer. RF electronics, IC design, radars, FPGA, programming. hforsten.com
Worked in most fields of Electronic Design Automation, sailor in my spare time, and have enough hobbies and interests to last me more than one lifetime :-)
I'm an aging tech nerd, avid hiker, a volunteer park docent, and geocacher. I recently retired after more than three decades working in electronic design automation.
I'm also on Mastodon at @sfba.social@not2b .
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